Row activation operations within a memory component are carried out with respect to
subrows instead of complete storage rows to reduce power consumption. Further, instead of …

A disclosed example apparatus includes a row address register (412) to store a row address
corresponding to a row (608) in a memory array (602). The example apparatus also includes …

In a memory module having a buffer component, a plurality of data signaling paths and a
plurality of memory dies each coupled to a respective one of the data signaling paths, the …

A method and system for a DRAM having a first bank that includes a first sub-array (SA) and
a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first …

A system or method for identifying latency contributors in a data storage network, that may
include creating a historical workload fingerprint model for a data storage network from …

Row activation operations within a memory component are carried out with respect to
subrows instead of complete storage rows to reduce power consumption. Further, instead of …

A system or method for identifying anomalies indicating misconfiguration or software bugs in
a data storage network that may include capturing data storage network latency metrics …

Described are motherboards with memory-module sockets that accept legacy memory
modules for backward compatibility, or accept a greater number of configurable modules in …

There is provided an apparatus that includes an input port to receive, from a requester, any
one of: a lookup operation comprising an input address, and a maintenance operation …

A resistive memory device includes a memory cell array, a memory interface and a read
sensing circuit. The memory cell array includes a plurality of resistive memory cells coupled …