Applications extensively use data objects with a regular and fixed layout, which leads to the
recurrence of access patterns over memory regions. Spatial data prefetching techniques …

Recent research advocates large die-stacked DRAM caches in many core servers to break
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …

The increasing demand for extracting value out of ever-growing data poses an ongoing
challenge to system designers, a task only made trickier by the end of Dennard scaling. As …

In the near future, die-stacked DRAM will be increasingly present in conjunction with off-chip
memories in hybrid memory systems. Research on this subject revolves around using the …

Hybrid main memories composed of DRAM and NonVolatile Memory (NVM) combine the
capacity benefits of NVM with the low-latency properties of DRAM. For highest performance …

To feed the high degrees of parallelism in modern graphics processors and manycore CPU
designs, DRAM manufacturers have created new DRAM architectures that deliver high …

This paper makes a case for a new cross-layer interface, Expressive Memory (XMem), to
communicate higher-level program semantics from the application to the system software …

Modern NUMA platforms offer large numbers of cores to boost performance through
parallelism and multi-threading. However, because performance scalability is limited by …

Efficient cache tag management is a primary design objective for large, in-package DRAM
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …

Data movement between memory and CPU is a well-known energy bottleneck for analytics.
Near-Memory Processing (NMP) is a promising approach for eliminating this bottleneck by …