Processing-in-memory: A workload-driven perspective

S Ghose, A Boroumand, JS Kim… - IBM Journal of …, 2019 - ieeexplore.ieee.org
Many modern and emerging applications must process increasingly large volumes of data.
Unfortunately, prevalent computing paradigms are not designed to efficiently handle such …

Alpaca: Intermittent execution without checkpoints

K Maeng, A Colin, B Lucia - Proceedings of the ACM on Programming …, 2017 - dl.acm.org
The emergence of energy harvesting devices creates the potential for batteryless sensing
and computing devices. Such devices operate only intermittently, as energy is available …

Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation

TE Carlson, W Heirman, L Eeckhout - Proceedings of 2011 International …, 2011 - dl.acm.org
Two major trends in high-performance computing, namely, larger numbers of cores and the
growing size of on-chip cache memory, are creating significant challenges for evaluating the …

NV-Heaps: Making persistent objects fast and safe with next-generation, non-volatile memories

J Coburn, AM Caulfield, A Akel, LM Grupp… - ACM SIGARCH …, 2011 - dl.acm.org
Persistent, user-defined objects present an attractive abstraction for working with non-
volatile program state. However, the slow speed of persistent storage (ie, disk) has restricted …

Chain: tasks and channels for reliable intermittent programs

A Colin, B Lucia - Proceedings of the 2016 ACM SIGPLAN International …, 2016 - dl.acm.org
Energy harvesting computers enable general-purpose computing using energy collected
from their environment. Energy-autonomy of such devices has great potential, but their …

A simpler, safer programming and execution model for intermittent systems

B Lucia, B Ransford - ACM SIGPLAN Notices, 2015 - dl.acm.org
Energy harvesting enables novel devices and applications without batteries, but intermittent
operation under energy harvesting poses new challenges to memory consistency that …

[HTML][HTML] The landscape of parallel computing research: A view from berkeley

K Asanovic, R Bodik, B Catanzaro, J Gebis… - 2006 - escholarship.org
The recent switch to parallel microprocessors is a milestone in the history of computing.
Industry has laid out a roadmap for multicore designs that preserves the programming …

Learning from mistakes: a comprehensive study on real world concurrency bug characteristics

S Lu, S Park, E Seo, Y Zhou - … of the 13th international conference on …, 2008 - dl.acm.org
The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately,
writing correct concurrent programs is difficult. Addressing this challenge requires advances …

{Prime+ Abort}: A {Timer-Free}{High-Precision} L3 Cache Attack using Intel {TSX}

C Disselkoen, D Kohlbrenner, L Porter… - 26th USENIX Security …, 2017 - usenix.org
Last-Level Cache (LLC) attacks typically exploit timing side channels in hardware, and thus
rely heavily on timers for their operation. Many proposed defenses against such side …

STAMP: Stanford transactional applications for multi-processing

CC Minh, JW Chung, C Kozyrakis… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
Transactional Memory (TM) is emerging as a promising technology to simplify parallel
programming. While several TM systems have been proposed in the research literature, we …