Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers
(AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes …

US9508417B2 - Methods and apparatuses for controlling timing paths and latency based on
a loop delay - Google Patents US9508417B2 - Methods and apparatuses for controlling …

Apparatuses and methods related to adjusting a minimum forward path delay of a signal
path are disclosed. One Such signal path includes a signal path having a minimum forward …

On the fly tuning of parameters used in an interface between a memory (eg high speed
memory Such as DRAM) and a processor requesting access to the memory. In an …

Apparatuses, integrated circuits, and methods are disclosed for synchronizing data signals
with a command signal. In one such example apparatus, an input control circuit is configured …

Command paths, apparatuses, and methods for providing a command to a data block are
described. In an example command path, a command receiver is configured to receive a …

An apparatus or method may include provision of a command to a data block. An example
apparatus includes a command circuit configured to provide a command signal in an …

Command paths, apparatuses, memories, and methods for providing an internal command
to a data path are disclosed. In an example method, a command is received and propagated …

US9531363B2 - Methods and apparatuses including command latency control circuit -
Google Patents US9531363B2 - Methods and apparatuses including command latency …

A read latency control circuit is described having a clock synchronization circuit and a read
latency control circuit. The clock synchronization circuit includes an adjustable delay line to …