With the rapid developments in VLSI technology, the communication channels in networks-
on-chip (NoCs) can place many wires for sustaining high-performance requirements over …

Duplication, misrouting, and dropping of packets due to short faults on network-on-chip
(NoC) interconnects have become a burden and significant impact on performance metrics …

Interconnect shorts in a network-on-chip (NoC) have caused data overloading and
misrouting that make an extra burden on performance metrics. Therefore, diagnosis of shorts …

Traditional bus-based systems-on-chip (SoCs) are turned to on-chip networks (NoCs) to
overcome communication bottleneck. But, fabricating such NoC-based systems without any …

A scalable, packet address driven strategy that tests an open fault on network-on-chip (NoC)
interconnects and maximal connectivity between neighbor routers in presence of a short …

Network-on-chip (NoC) has currently considered as a holistic solution over traditional and
global bus-based system-on-chip (SoC) interconnections. However, NoC interconnects …

This paper presents a distributed on-line test mechanism that detects stuck-at faults (SAFs)
in the channels as well as identifies the faulty channel-wires in an on-chip network (NoC) …

With the continuous growth in technology, the role of nano-electronic systems is rapidly
expanding in every facet of modern life. Subsequently, the demand of high performance …

In an on-chip network (NoC), the channels often experience several open faults because of
certain manufacturing or in-field defects. Such faults may cause enormous loss of packets …

With the ever-shrinking global geometries on a die and the concomitant rise in the
complexity of interconnections in an on-chip network (NoC), the links used therein often …