Design of ternary logic circuits using pseudo N-type CNTFETs

SV RatanKumar, LK Rao… - ECS Journal of Solid State …, 2022 - iopscience.iop.org
In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics
applications. The ternary logic is a best alternative to the binary logic because it offers …

Design of quaternary min and max circuits using graphene nanoribbon field effect transistors

SJ Basha, P Venkatramana - Materials Today: Proceedings, 2022 - Elsevier
This paper presents the design of digital logic schematics in quaternary logic. The
quaternary logic is considered as best choice over the conventional two-valued logic due to …

Design of bilayer graphene nanoribbon tunnel field effect transistor

RK Vobulapuram, JB Shaik, VP, DP Mekala… - Circuit World, 2023 - emerald.com
Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET)
using graphene nanoribbons (GNRs). Design/methodology/approach To design the …

[HTML][HTML] Design, simulation and comparative analysis of carbon nanotube based energy efficient priority encoders for nanoelectronic applications

IA Khan, A Rai, JP Keshari, M Nizamuddin… - e-Prime-Advances in …, 2023 - Elsevier
In the paper, innovative CNT based encoder and two priority encoders have been designed,
simulated and compared with conventional CMOS encoder and priority encoders at 32 nm …

[HTML][HTML] Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

SV RatanKumar, LK Rao, MK Kumar - e-Prime-Advances in Electrical …, 2023 - Elsevier
Now-a-days, the binary logic system has intensified by scaling the field effect transistor
(FET). However, due to the effectiveness of scaling the FET, ternary logics became more …

Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques

TNJ Kolanti… - International Journal of …, 2020 - Wiley Online Library
This paper presents an accurate structure for multilayer graphene nanoribbon (MLGNR)
bundled interconnects to reduce the effects of crosstalk in ternary logic circuits. In the …

Design of Ternary Multiplier Using Pseudo NCNTFETs

SV Ratan Kumar, L Koteswara Rao… - Russian …, 2023 - Springer
A novel technique is proposed in this paper to design ternary logic circuits for
nanoelectronics applications. The ternary logic is a best alternative to the binary logic …

Design of SB-GNRFET and D-GNRFET using QuantumATK

P Venkatramana, P Nagarajan… - … on Networking and …, 2023 - ieeexplore.ieee.org
In recent days, graphene nanoribbon field-effecttransistors (GNRFETs) are considered as
promising candidate in semiconductor technology because it's outstanding properties such …

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices.

IA Khan, M Shahid, JP Keshari… - … Modelling of Engineering …, 2023 - search.ebscohost.com
Error-free communication is crucial for modern electronic devices. Error detection and
correction mechanisms are essential to ensure accurate information transmission. With the …

[HTML][HTML] Design of low power high-speed full, swing 11T CNTFET adder

B Anjaneyulu, NSS Reddy - e-Prime-Advances in Electrical Engineering …, 2024 - Elsevier
As the semiconductor industry continues to decrease in size, it faces many issues, such as
scalability, leakage, short-channel effects, and reliability. carbon nanotubes (CNT) has …