Flexible high throughput QC-LDPC decoder with perfect pipeline conflicts resolution and efficient hardware utilization
VL Petrović, MM Marković… - … on Circuits and …, 2020 - ieeexplore.ieee.org
Modern communication standards, such as 5G new radio (5G NR), require a high speed
decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely …
decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely …
High-speed LDPC decoders towards 1 Tb/s
Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant
challenge to the channel decoder. In this paper, we propose a multi-core architecture based …
challenge to the channel decoder. In this paper, we propose a multi-core architecture based …
Design of high-performance and area-efficient decoder for 5G LDPC codes
H Cui, F Ghaffari, K Le, D Declercq… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Low-density parity-check (LDPC) code as a very promising error-correction code has been
adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is …
adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is …
An FPGA-based LDPC decoder with ultra-long codes for continuous-variable quantum key distribution
SS Yang, JQ Liu, ZG Lu, ZL Bai, XY Wang, YM Li - IEEE Access, 2021 - ieeexplore.ieee.org
In this paper, we propose a good decoding performance, low-complexity, and high-speed
decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum …
decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum …
Decision-directed retention-failure recovery with channel update for MLC NAND flash memory
To recover from the retention noise induced errors in nand flash memory, a retention-aware
belief-propagation (RABP) decoding scheme for low-density parity-check codes is …
belief-propagation (RABP) decoding scheme for low-density parity-check codes is …
A high-efficiency segmented reconfigurable cyclic shifter for 5G QC-LDPC decoder
A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for
5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one …
5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one …
Hardware-friendly LDPC decoding scheduling for 5G HARQ applications
This paper presents hardware-friendly LDPC decoding schedules for 5G hybrid automatic
repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity …
repeat request (HARQ) applications. Since there are built-in punctured blocks in the parity …
A 5.28-Gb/s LDPC decoder with time-domain signal processing for IEEE 802.15. 3c applications
This paper presents a high-throughput, energy-efficient, and scalable low-density parity-
check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter …
check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter …
Dispersed array LDPC codes and decoder architecture for NAND flash memory
W Shao, J Sha, C Zhang - … on Circuits and Systems II: Express …, 2017 - ieeexplore.ieee.org
Quasi-cyclic (QC) low-density parity-check (LDPC) codes have become popular in NAND
flash memories, owing to their excellent error correction performance and hardware-friendly …
flash memories, owing to their excellent error correction performance and hardware-friendly …
Efficient layered parallel architecture and application for large matrix ldpc decoder
J Wang, J Yang, G Zhang, X Zeng, Y Chen - Electronics, 2023 - mdpi.com
For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder,
decoding performance and area efficiency must be balanced. This paper adopts a layered …
decoding performance and area efficiency must be balanced. This paper adopts a layered …