With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Fast and accurate pre-routing timing prediction is essential for timing-driven placement since
repetitive routing and static timing analysis (STA) iterations are expensive and …

Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

IR drop constraint is a fundamental requirement enforced in almost all chip designs.
However, its evaluation takes a long time, and mitigation techniques for fixing violations may …

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …

Timing estimation prior to routing is of vital importance for optimization at placement stage
and timing closure. Existing wire-or net-oriented learning-based methods limits the accuracy …

Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly
used in several fields to improve performance and the level of automation. In recent years …

Modern designs are increasingly reliant on physical design (PD) tools to derive full
technology scaling benefits of Moore's Law. Designers often perform power, performance …

Recently, deep-learning (DL) models have paid a considerable attention to timing prediction
in the placement and routing (P&R) flow. As yet, the DL-based prior works are confined to …

Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …