A survey of the RISC-V architecture software support
RISC-V is a novel open instruction set architecture that supports multiple platforms while
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
Fault injection of TMR open source RISC-V processors using dynamic partial reconfiguration on SRAM-based FPGAs
AE Wilson, M Wirthlin - 2021 IEEE Space Computing …, 2021 - ieeexplore.ieee.org
SRAM-based FPGAs are frequently used for critical functions in space applications. Soft
processors implemented within these FPGAs are often needed to satisfy the mission …
processors implemented within these FPGAs are often needed to satisfy the mission …
Early soft error reliability analysis on RISC-V
N Lodéa, W Nunes, V Zanini, M Sartori… - IEEE Latin America …, 2022 - ieeexplore.ieee.org
The adoption of RISC-V processors bloomed in recent years, mainly due to its open
standard and free instruction set architecture. However, much remains to help software …
standard and free instruction set architecture. However, much remains to help software …
Hardening a real-time operating system for a dependable risc-v system-on-chip
In safety-critical systems, solutions that rely on redundancies at the hardware and software
levels allow these systems to operate in radiation-harsh environments. In the literature …
levels allow these systems to operate in radiation-harsh environments. In the literature …
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors
S Shukla, M Azam, KC Ray - IEEE Transactions on Circuits …, 2023 - ieeexplore.ieee.org
In the modern era, FPGA-based soft-core processors have gained much attention in space
applications due to their flexibility and ease of integration. In such applications, radiation can …
applications due to their flexibility and ease of integration. In such applications, radiation can …
Soft error assessment of CNN inference models running on a RISC-V processor
Software engineers use different compilers and code optimisation levels (eg, O2 and Os) to
achieve the best results considering distinguish constraints (eg, power, performance and …
achieve the best results considering distinguish constraints (eg, power, performance and …
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
BE Forlin, W van Huffelen, C Cazzaniga… - 2023 IEEE European …, 2023 - ieeexplore.ieee.org
Fast development, low cost, and reconfigurability are becoming critical factors for aerospace
applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in …
applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in …
Softprocessor riscv-ec for edge computing applications
Hard-processors are those that have their architecture defined from the factory and this
makes them less flexible in the face of architecture changes while softprocessors have the …
makes them less flexible in the face of architecture changes while softprocessors have the …
The characterization of errors in an FPGA-based RISC-V processor due to single event transients
J Sharma, N Rao - Microelectronics Journal, 2022 - Elsevier
The reliability of processors is a crucial aspect of processor design. In this study, we design
a fault injection framework based on Single Event Transients (SET) to understand its impact …
a fault injection framework based on Single Event Transients (SET) to understand its impact …
Guillermo Montesdeoca¹, Víctor Asanza¹®, Rebeca Estrada¹ ()
I Valeriano¹, MA Muneeb - Innovative Mobile and Internet …, 2023 - books.google.com
Hard-processors are those that have their architecture defined from the factory and this
makes them less flexible in the face of architecture changes while softprocessors have the …
makes them less flexible in the face of architecture changes while softprocessors have the …