BACKGROUND This invention relates generally to computer memory and more particularly,
to heterogeneous recovery in a redundant memory system. Redundant array of independent …

A memory system includes: a memory controller including an error correction decoder. The
error correction decoder includes: a demultiplexer adapted to receive data and demultiplex …

2. Description of the Related Art Mass storage devices may include a number of memory
devices, such as NAND memory devices, NOR memory devices, phase change devices …

US8522122B2 - Correcting memory device and memory channel failures in the presence of
known memory device failures - Google Patents US8522122B2 - Correcting memory device …

Error correction and detection in a redundant memory system that includes a memory
controller; a plurality of memory channels in communication with the memory controller, the …

Protecting in-memory configuration state registers. A request to access an in-memory
configuration state register, such as a read or write request, is obtained. The in-memory …

Providing homogeneous recovery in a redundant memory system that includes a memory
controller, a plurality of memory channels in communication with the memory controller, an …

Portions of configuration state registers in-memory. An instruction is obtained, and a
determination is made that the instruction accesses a configuration state register. A portion …

Bulk store and load operations of configuration state regis ters. An instruction to perform a
bulk operation for a group of configuration state registers having a common character istic is …

Configurable architectural placement control. A control is provided that specifies a location
in memory at which one or more in-memory configuration state registers are stored. The …