A survey on lifting-based discrete wavelet transform architectures
T Acharya, C Chakrabarti - Journal of VLSI signal processing systems for …, 2006 - Springer
In this paper, we review recent developments in VLSI architectures and algorithms for
efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic …
efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic …
A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants
This paper describes an area and power-efficient VLSI approach for implementing the
discrete wavelet transform on streaming multielectrode neurophysiological data in real time …
discrete wavelet transform on streaming multielectrode neurophysiological data in real time …
Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform
Memory requirements (for storing intermediate signals) and critical path are essential issues
for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware …
for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware …
Channel state reconstruction using multilevel discrete wavelet transform for improved fingerprinting-based indoor localization
Recently, channel state information (CSI) has been adopted as an enhanced wireless
channel measurement instead of received signal strength (RSS) for indoor WiFi positioning …
channel measurement instead of received signal strength (RSS) for indoor WiFi positioning …
A systems approach for data compression and latency reduction in cortically controlled brain machine interfaces
KG Oweiss - IEEE Transactions on Biomedical Engineering, 2006 - ieeexplore.ieee.org
This paper suggests a new approach for data compression during extracutaneous
transmission of neural signals recorded by high-density microelectrode array in the cortex …
transmission of neural signals recorded by high-density microelectrode array in the cortex …
An efficient non-separable architecture for Haar wavelet transform with lifting structure
SA Bamerni, AK Al-Sulaifanie - Microprocessors and Microsystems, 2019 - Elsevier
In this paper, a memory efficient, fully integer to integer with parallel architecture for 2-D
Haar wavelet transform with lifting scheme has been proposed. The main problem in most 2 …
Haar wavelet transform with lifting scheme has been proposed. The main problem in most 2 …
High-performance hardware architectures for multi-level lifting-based discrete wavelet transform
AD Darji, SS Kushwah, SN Merchant… - EURASIP Journal on …, 2014 - Springer
In this paper, three hardware efficient architectures to perform multi-level 2-D discrete
wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are …
wavelet transform (DWT) using lifting (5, 3) and (9, 7) filters are presented. They are …
SPIHT algorithm with adaptive selection of compression ratio depending on DWT coefficients
In mobile multimedia devices, the frame memory compression (FMC) technique by
embedded compression (EC) is becoming an increasingly important video-processing …
embedded compression (EC) is becoming an increasingly important video-processing …
VLSI architecture of line-based lifting wavelet transform for motion JPEG2000
In this paper, we proposed a new architecture of lifting processor for JPEG2000 and
implemented it with both FPGA and ASIC. It includes a new cell structure that executes a unit …
implemented it with both FPGA and ASIC. It includes a new cell structure that executes a unit …
A new discrete wavelet transform appropriate for hardware implementation
A Meshkat, R Dehghani - International Journal of Circuit Theory …, 2020 - Wiley Online Library
A new method for computation of discrete wavelet transform is introduced. The impulse
response of the finite impulse response (FIR) filter, as the main block in filter bank method, is …
response of the finite impulse response (FIR) filter, as the main block in filter bank method, is …