SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

J Guo, L Wang, Y Yu, P Wang, Y Huang… - Advanced …, 2019 - Wiley Online Library
The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage
operation and lower power consumption, both critical for mobile devices and internet of …

Mixed‐Dimensional MoS2/Ge Heterostructure Junction Field‐Effect Transistors for Logic Operation and Photodetection

B Wang, L Wang, Y Zhang, M Yang… - Advanced Functional …, 2022 - Wiley Online Library
There has been a growing interest in electronic and optoelectronic devices based on
heterostructures between atomically thin 2D and 3D semiconductor materials. This paper …

High-temperature operation of diamond junction field-effect transistors with lateral pn junctions

T Iwasaki, Y Hoshino, K Tsuzuki, H Kato… - IEEE Electron …, 2013 - ieeexplore.ieee.org
High-temperature performance of diamond junction field-effect transistors (JFETs) with
lateral pn junctions is demonstrated. Diamond JFETs fabricated by n-type selective growth …

Recent advances in two-dimensional p-type metal chalcogenides: synthesis, doping strategies and applications

J Wu, F Zhuge, H Li, T Zhai - Journal of Physics D: Applied …, 2022 - iopscience.iop.org
Abstract Two-dimensional (2D) metal chalcogenides (MCs) showed great potential in
meeting the requirements of high-performance (opto) electronic devices. In addition to the …

J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications

SE Yu, HJ Lee, M Kim, S Im, YT Lee - ACS nano, 2024 - ACS Publications
High-performance and low operating voltage are becoming increasingly significant device
parameters to meet the needs of future integrated circuit (IC) processors and ensure their …

Thinning Solution‐proceed 2D Te for p‐and n‐channel Junction Field Effect Transistor with High Mobility and Ideal Subthreshold Slope

L Zhu, J Zhang, X Chen, N Bu, T Zheng… - Advanced Functional …, 2024 - Wiley Online Library
Two‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in
transistor applications because of its high carrier mobility and air stability. However, it is still …

An analytical drain current modelling of DMGC CGAA FET: a circuit level implementation

PK Mudidhe, BR Nistala - Physica Scripta, 2023 - iopscience.iop.org
The GAA FET has emerged as a promising device due to its excellent control over short-
channel effects and improved electrostatic control. This manuscript presents the analytical …

Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance

V Kumari, N Modi, M Saxena… - IEEE transactions on …, 2015 - ieeexplore.ieee.org
In this paper, we report the 2-D drain current model for asymmetric dual material (DM)
junctionless double gate transistor. On the basis of channel potential, transconductance and …

Empirical model for nonuniformly doped symmetric double-gate junctionless transistor

V Kumari, A Kumar, M Saxena… - IEEE transactions on …, 2017 - ieeexplore.ieee.org
This paper demonstrates the influence of nonuniform doping on the electrostatics of
symmetric double-gate junctionless transistor using empirical modeling scheme. To present …

Two-dimensional analytical drain current model for double-gate MOSFET incorporating dielectric pocket

V Kumari, M Saxena, RS Gupta… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-
power applications. A complete drain current model has been developed including the …