Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems
M Trik, S Pour Mozaffari… - Computational …, 2021 - Wiley Online Library
Effective and efficient routing is one of the most important parts of routing in NoC‐based
neuromorphic systems. In fact, this communication structure connects different units through …
neuromorphic systems. In fact, this communication structure connects different units through …
An adaptive routing strategy to reduce energy consumption in network on chip
Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have
been able to handle the communication between processing cores, inspired by computer …
been able to handle the communication between processing cores, inspired by computer …
High‐efficient circuits for ternary addition
New ternary adders, which are fundamental components of ternary addition, are presented
in this paper. They are on the basis of a logic style which mostly generates binary signals …
in this paper. They are on the basis of a logic style which mostly generates binary signals …
HREN: A hybrid reliable and energy-efficient network-on-chip architecture
P Bhamidipati, A Karanth - IEEE Transactions on Emerging …, 2022 - ieeexplore.ieee.org
As transistor scales down to sub-nanometer and processing cores with billions of transistors
are integrated, reliable and energy-efficient Network-on-Chip (NoC) architectures are critical …
are integrated, reliable and energy-efficient Network-on-Chip (NoC) architectures are critical …
An improved low-power coding for serial network-on-chip links
S Velayudham, S Rajagopal, SB Ko - Circuits, Systems, and Signal …, 2020 - Springer
In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant
research solution to on-chip multiprocessor-based real-time applications. As the number of …
research solution to on-chip multiprocessor-based real-time applications. As the number of …
Fuzzy-based mapping algorithms to design networks-on-chip
Abstract Network on Chip (NoC) has been suggested as an appropriate and scalable
solution for System on Chip (SoC) architectures having high communication demands. In …
solution for System on Chip (SoC) architectures having high communication demands. In …
Optimization approaches for core mapping on networks on chip
ABSTRACT Network on Chip (NoC) has been suggested as an appropriate solution for the
communication demands in Systems on Chip (SoCs). Due to the limitation of the resources …
communication demands in Systems on Chip (SoCs). Due to the limitation of the resources …
Crosstalk aware transient error correction coding technique for NoC links
M Vinodhini, NS Murty, TK Ramesh - Microelectronics Reliability, 2021 - Elsevier
Abstract In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect
design are to meet the performance, power consumption requirements of the SoC and to …
design are to meet the performance, power consumption requirements of the SoC and to …
Low energy yet reliable data communication scheme for network-on-chip
N Jafarzadeh, M Palesi, S Eskandari… - … on Computer-Aided …, 2015 - ieeexplore.ieee.org
In this paper, a low energy yet reliable communication scheme for network-on-chip is
suggested. To reduce the communication energy consumption, we invoke low-swing signals …
suggested. To reduce the communication energy consumption, we invoke low-swing signals …
RETRACTED ARTICLE: Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC
B Subramaniam, S Muthusamy, G Gengavel - Journal of Ambient …, 2021 - Springer
A number of bus encoding techniques are renowned in low power dissipation of network-on-
chip. The objective of the proposed algebraic framework dual binary weighted code (DBWC) …
chip. The objective of the proposed algebraic framework dual binary weighted code (DBWC) …