Microarchitecture design and verification of co-processor for floating point operation

K Harshitha, AS Hithen, TAJ Madappa… - Recent Trends in …, 2023 - taylorfrancis.com
In the microprocessor's chip, additional circuits can be introduced for unique purposes to
execute particular tasks or to carry out numerical operations to offload work from the main …

A Survey on Floating Point Arithmetic Units for Non-Linear Application

KG Pande, PT Karule - … on Emerging Trends in Engineering and …, 2022 - ieeexplore.ieee.org
This paper contributes to the comprehensive study of floating point arithmetic. It lists many
researchers' contributions to improving the general functionality of floating point arithmetic …

[PDF][PDF] Design of a Novel Fused Add-Sub Module for IEEE 754-2008 Floating Point Unit in High Speed Applications

A Bisoyi, A Tripathy - Comm Appl Electron, 2020 - researchgate.net
ABSTRACT A multiplier block can be implemented either by shift add technique, Booth
algorithm or Vedic algorithm, in DSP applications. However, these techniques do not work …

Design and Synthesis of a 256-Point Radix-2 DIT FFT Core with Design Ware Library using Fixed-Point Number Representation

D Krishnegowda, P Nagaraju - 2022 IEEE Delhi Section …, 2022 - ieeexplore.ieee.org
In digital image processing, a time-domain image is converted to the frequency domain to
carry out operations such as image enhancing or noise reduction. Discrete time domain …

[PDF][PDF] FPGA-BASED DESIGN OF A MATH CO-PROCESSOR FOR THE AMIR CPU

ATANFOO YEN - 2020 - eprints.utm.my
Math coprocessors are vital components in modern computing to improve the overall
performance of the system. The AMIR CPU is a homegrown softcore 32-bit CPU that can …