[图书][B] Memory issues in embedded systems-on-chip: optimizations and exploration
Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed
for different groups in the embedded systems-on-chip arena. First, it is designed for …
for different groups in the embedded systems-on-chip arena. First, it is designed for …
Efficient exploration of the SoC communication architecture design space
In this paper, we present a methodology and efficient algorithms for the design of high-
performance system-on-chip communication architectures. Our methodology automatically …
performance system-on-chip communication architectures. Our methodology automatically …
Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines
J Park, PC Diniz - Proceedings of the 14th international symposium on …, 2001 - dl.acm.org
Commercially available behavioral synthesis tools do not adequately support FPGA vendor-
specific external memory interfaces making it extremely difficult to exploit pipelined memory …
specific external memory interfaces making it extremely difficult to exploit pipelined memory …
A design methodology to implement memory accesses in high-level synthesis
C Pilato, F Ferrandi, D Sciuto - Proceedings of the seventh IEEE/ACM …, 2011 - dl.acm.org
Nowadays, the memory synthesis is becoming the main bottleneck for the generation of
efficient hardware accelerators. This paper presents a design methodology to efficiently and …
efficient hardware accelerators. This paper presents a design methodology to efficiently and …
Reverse-engineering embedded memory controllers through latency-based analysis
We explore techniques to reverse-engineer properties of DRAM memory controllers (MCs).
This includes page policies, address mapping schemes and command arbitration schemes …
This includes page policies, address mapping schemes and command arbitration schemes …
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer
memory modules exhibiting efficient access modes (eg, page-, burst-mode) partly alleviate …
memory modules exhibiting efficient access modes (eg, page-, burst-mode) partly alleviate …
Impact of DRAM refresh on the execution time of real-time tasks
P Atanassov, P Puschner - Proceedings of the International …, 2001 - repositum.tuwien.at
In this paper we discuss how DRAM refreshes influence the execution times and the Worst-
Case Execution-Time (WCET) analysis of real-time programs executed on platforms that use …
Case Execution-Time (WCET) analysis of real-time programs executed on platforms that use …
Optimizing the memory bandwidth with loop fusion
P Marchal, JI Gómez, F Catthoor - Proceedings of the 2nd IEEE/ACM/IFIP …, 2004 - dl.acm.org
The memory bandwidth largely determines the performance and energy cost of embedded
systems. At the compiler level, several techniques improve the memory bandwidth at the …
systems. At the compiler level, several techniques improve the memory bandwidth at the …
Optimal data transfer and buffering schemes for JPEG2000 encoder
MY Chiu, KB Lee, CW Jen - 2003 IEEE Workshop on Signal …, 2003 - ieeexplore.ieee.org
The paper presents optimal data transfer and buffering schemes for a JPEG2000 encoder.
The data transfer scheme combines bit-level zero run-length coding and addressing mode …
The data transfer scheme combines bit-level zero run-length coding and addressing mode …
MIST: An algorithm for memory miss traffic management
Cache misses represent a major bottleneck in embedded systems performance.
Traditionally, compilers optimistically treated all memory accesses as cache hits, relying on …
Traditionally, compilers optimistically treated all memory accesses as cache hits, relying on …