Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study

J Ajayan, D Nirmal, S Tayal, S Bhattacharya… - Microelectronics …, 2021 - Elsevier
Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-
around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects …

Future logic scaling: Towards atomic channels and deconstructed chips

SB Samavedam, J Ryckaert, E Beyne… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
With each new node, cost and complexity of logic technology increases while being
challenged to provide the historical expected improvement in performance. This paper …

Progress and future prospects of negative capacitance electronics: A materials perspective

M Hoffmann, S Slesazeck, T Mikolajick - APL Materials, 2021 - pubs.aip.org
Negative capacitance in ferroelectric materials has been suggested as a solution to reduce
the power dissipation of electronics beyond fundamental limits. The discovery of …

Moore's law: the journey ahead

MS Lundstrom, MA Alam - Science, 2022 - science.org
The transistor was invented 75 years ago, and the integrated circuit (IC) soon thereafter. The
progress in making transistors smaller also led to them becoming cheaper, which was …

Design insights of nanosheet FET and CMOS circuit applications at 5-nm technology node

VB Sreenivasulu, V Narendar - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and
nanosheet (NS) FETs performance are estimated with equal effective channel widths () at …

Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI

G Hills, MG Bardon, G Doornbos… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the
energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated …

Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes

D Nagy, G Espineira, G Indalecio… - IEEE …, 2020 - ieeexplore.ieee.org
Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (LG) of 16 nm
and below are benchmarked against equivalent FinFETs. The device performance is …

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …

Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration

H Mertens, R Ritzenthaler, V Pena… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW)
MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We …

Performance evaluation of GAA nanosheet FET with varied geometrical and process parameters

NA Kumari, P Prithvi - Silicon, 2022 - Springer
Abstract Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in
sub-7-nm technology. This paper provides insights into the variations of DC FOMs for …