A Comparative Study of FIR Filters using Vedic and Booths Algorithm
A Agarwal, S Mitra, S Dutta - 2016 8th International Conference …, 2016 - ieeexplore.ieee.org
In this paper step by step procedure for the construction of a high speed FIR filter is
developed based on the concept of Vedic mathematics as well as modified Booth Wallace …
developed based on the concept of Vedic mathematics as well as modified Booth Wallace …
Bit-serial linear algebra processor
The invention is notably directed to a computing system configured to perform linear
algebraic operations. The com puting system comprises a co-processing module compris …
algebraic operations. The com puting system comprises a co-processing module compris …
Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs
S Guo, Y Dou, Y Lei - Computer Engineering and Technology: 18th CCF …, 2015 - Springer
This paper proposes a fully pipelined dual-mode double precision floating-point reduction
circuit on the field programming gate arrays (FPGAs), which is capable of supporting one …
circuit on the field programming gate arrays (FPGAs), which is capable of supporting one …