The challenges of advanced CMOS process from 2D to 3D
HH Radamson, Y Zhang, X He, H Cui, J Li, J Xiang… - Applied Sciences, 2017 - mdpi.com
The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit
bricks in integrated circuits (ICs) have constantly changed during the past five decades. The …
bricks in integrated circuits (ICs) have constantly changed during the past five decades. The …
Insight into gate-induced drain leakage in silicon nanowire transistors
J Fan, M Li, X Xu, Y Yang, H Xuan… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-
around silicon nanowire transistors (SNWTs) are investigated and verified by experiments …
around silicon nanowire transistors (SNWTs) are investigated and verified by experiments …
Review of advanced CMOS technology for post-Moore era
M Li - Science China Physics, Mechanics and Astronomy, 2012 - Springer
The continuous downsizing of device has sustained Moore's law in the past 40 years. As the
power dissipation becomes more and more serious, a lot of emerging technologies have …
power dissipation becomes more and more serious, a lot of emerging technologies have …
Controlling the wet-etch directionality in nanostructured silicon
Anisotropic wet etching of crystalline silicon (c-Si) is a key chemical process used in
microelectronic device fabrication. Controlled fabrication of c-Si nanostructures requires an …
microelectronic device fabrication. Controlled fabrication of c-Si nanostructures requires an …
Gate-induced drain leakage reduction in cylindrical dual-metal hetero-dielectric gate all around MOSFET
In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all
around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate …
around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate …
Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device …
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
Performance optimization of high-K GAA-PZT Negative Capacitance FET MFIS Silicon Nanowire for low power RFIC and analog applications
Abstract In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA
PZT-NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the …
PZT-NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the …
[HTML][HTML] Compact modeling of quantum confinements in nanoscale gate-all-around MOSFETs
B Peng, Y Jiao, H Zhong, Z Rong, Z Wang, Y Xiao… - Fundamental …, 2024 - Elsevier
In this work, a surface-potential based compact model focusing on the quantum confinement
effects of ultimately scaled gate-all-around (GAA) MOSFET is presented. Energy …
effects of ultimately scaled gate-all-around (GAA) MOSFET is presented. Energy …
Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part I–modeling and simulation method
In this paper, the correlation between line-edge roughness (LER) and line-width roughness
(LWR) is investigated. Based on the characterization methodology of auto-correlation …
(LWR) is investigated. Based on the characterization methodology of auto-correlation …
Dual-gate silicon nanowire FET with a corner spacer for high-performance and high-frequency applications
Parasitic capacitance in extremely scaled devices is a major issue in device/circuit design.
Its contribution to the total device capacitance is very large, especially in nanowire field …
Its contribution to the total device capacitance is very large, especially in nanowire field …