A gracefully degrading and energy-efficient fault tolerant NoC using spare core

BNK Reddy, MH Vasantha… - 2016 IEEE computer …, 2016 - ieeexplore.ieee.org
Reliability is a significant strategy concern for modern day multi core embedded systems. On
chip communicating systems are vulnerable to permanent network faults and transient faults …

High-performance and energy-efficient fault-tolerance core mapping in NoC

NKR Beechu, VM Harishchandra… - … : Informatics and Systems, 2017 - Elsevier
Abstract Network on Chip (NoC) has been proposed as an efficient solution to
communication problems in on-chip processors. The probability of failure increases in these …

Runtime techniques to mitigate soft errors in network-on-chip (NoC) architectures

T Boraten, AK Kodi - … on Computer-Aided Design of Integrated …, 2017 - ieeexplore.ieee.org
As aggressive scaling continues to push multiprocessor system-on-chips (MPSoCs) to new
limits, complex hardware structures combined with stringent area and power constraints will …

Transient error correction coding scheme for reliable low power data link layer in NoC

M Vinodhini, NS Murty, TK Ramesh - IEEE Access, 2020 - ieeexplore.ieee.org
Ensuring reliable data transmission in multicore System on Chip (SoC), which employs
Network on Chip (NoC), is a challenging task. This task is well addressed by Error …

An online and real-time fault detection and localization mechanism for network-on-chip architectures

K Chrysanthou, P Englezakis, A Prodromou… - ACM Transactions on …, 2016 - dl.acm.org
Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability
threats. The need to detect and localize the occurrence of faults at runtime is steadily …

A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance

M Vinodhini, K Lillygrace… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
This paper proposes fault tolerant Network on Chip (NoC) architecture which enables
switching of error control coding scheme present in data link layer and network layer as …

[图书][B] Hardware Security Threat and Mitigation Techniques for Network-on-Chips

TH Boraten - 2020 - search.proquest.com
Today, hardware security for state-of-the-art integrated circuits (ICs) is a growing concern
because semi-conductor supply-chains are increasingly complex and the industry is shifting …

Optimizing the location of ECC protection in network-on-chip

J Wang, L Huang, Q Li, G Li, A Jantsch - … of the Eleventh IEEE/ACM/IFIP …, 2016 - dl.acm.org
The communication in Network-on-Chips (NoCs) may be subject to errors. Error Correcting
Codes (ECCs) can be used to tolerate the transient faults in flits caused by Single Event …

Micro-architecture design for low overhead fault tolerant network-on-chip

C Yuan, L Huang, J Wang, Q Li - 2018 IEEE international …, 2018 - ieeexplore.ieee.org
Aggressive technology scaling results in reliability decrease of Network-on-Chips (NoCs).
Error Correction Codes (ECC) is commonly used to correct error data. It is necessary to …

Semiconductor devices executing an error scrub operation

JI Lee, YM Kim - US Patent 10,430,274, 2019 - Google Patents
A semiconductor device includes a flag generation circuit and a write operation circuit. The
flag generation circuit generates an error scrub flag if an error scrub operation is performed …