In this paper, a hierarchical optimization methodology for charge pump phase-locked loops
(CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient …

A comprehensive performance space exploration on system level offers designers a fast
way to get insight into the capability of the whole system for a given technology. The authors …

Advances in silicon technology over the last decade have led to increased integration of
analogue and digital functional blocks onto the same single chip. In such a mixed signal …

In order to reduce the power consumption of a system-on-chip, analog circuits can be
switched off when not needed with the help of power-down switches. The power-down …

In this thesis, a hierarchical optimization methodology based on Pareto-optimal front is
proposed for large-scale analog/mixed circuits, eg PLLs and sigma-delta modulators. At …

Current Verilog-AMS system level modeling does not capture the physical design (layout)
information of the target design as it is meant to be fast behavioral simulation only. Thus, the …

Electronic circuit behavioral models built with hardware description/modeling languages
such as Verilog-AMS for system-level simulations are typically functional models. They do …

As malhas de captura de fase (PLLs) são sistemas de realimentação negativa, cuja a fun-
ção é reduzir a diferença de fase entre o sinal de referência e o sinal na saída do oscilador …

This research addresses problems in designing analog and mixed-signal (AMS) systems by
bridging the gap between system-level and circuit-level simulation by making simulations …

A new approach in hierarchical optimisation is presented which is capable of optimising
both the performance and yield of an analogue design. Performance and yield trade offs are …