Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options
C Yoo, J Chang, Y Seon, H Kim… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Self-heating effects (SHEs) of multi-nanosheet FET (mNS-FET) at the 3-nm technology node
were analyzed at the device and circuit level considering the introduction of punchthrough …
were analyzed at the device and circuit level considering the introduction of punchthrough …
Self-heating and electrothermal properties of advanced sub-5-nm node nanoplate FET
I Myeong, I Song, MJ Kang… - IEEE Electron Device …, 2020 - ieeexplore.ieee.org
In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect
transistor (FET) with variations of active area specifications including number of vertically …
transistor (FET) with variations of active area specifications including number of vertically …
Analysis of self heating effect in DC/AC mode in multi-channel GAA-field effect transistor
I Myeong, D Son, H Kim, H Shin - IEEE transactions on electron …, 2019 - ieeexplore.ieee.org
In this article, the self-heating effect (SHE) of both dc and ac for a three-channel nanowire-
field effect transistor (FET) is investigated and analyzed. In the dc mode, as (definition: K) …
field effect transistor (FET) is investigated and analyzed. In the dc mode, as (definition: K) …
Compact model strategy of metal-gate work-function variation for ultrascaled FinFET and vertical GAA FETs
In this paper, we develop an accurate compact model for work-function variation (WFV)-
induced threshold voltage (Vth) variations of various 5-nm candidates, in this case, Si SOI …
induced threshold voltage (Vth) variations of various 5-nm candidates, in this case, Si SOI …
New insight into negative bias temperature instability degradation during self-heating in nanoscale bulk FinFETs
D Son, K Hong, H Shim, S Pae… - IEEE Electron Device …, 2019 - ieeexplore.ieee.org
In this letter, we investigate the threshold voltage shift (ΔV th) by negative bias temperature
instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk p-FinFET. To …
instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk p-FinFET. To …
Investigation of self-heating effects in vacuum gate dielectric gate-all-around vertically stacked silicon nanowire field effect transistors
Y Su, J Lai, L Sun - IEEE Transactions on Electron Devices, 2020 - ieeexplore.ieee.org
The self-heating effects in vacuum gate dielectric gate-all-around field effect transistors (GAA
FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D …
FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D …
Investigation of gate sidewall spacer optimization from OFF-state leakage current perspective in 3-nm node device
D Ryu, I Myeong, JK Lee, M Kang… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this paper, the structural and material optimization of gate sidewall spacer in the
perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET …
perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET …
Structural optimization of a junctionless VSTB FET to improve its electrical and thermal performance
This article provides an insight into the electrical and thermal performance improvement of a
junctionless vertical super-thin body (JL VSTB) FET based on dimensional and material …
junctionless vertical super-thin body (JL VSTB) FET based on dimensional and material …
Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing in Various Sub-10-nm 3-D Transistors
I Myeong, D Son, H Kim, M Kang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In this paper, we have devised on shallow trench isolation (STI) design considering leakage
current () in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The tendency is …
current () in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The tendency is …