Unsupervised person image synthesis in arbitrary poses

A Pumarola, A Agudo, A Sanfeliu… - Proceedings of the …, 2018 - openaccess.thecvf.com
We present a novel approach for synthesizing photo-realistic images of people in arbitrary
poses using generative adversarial learning. Given an input image of a person and a …

DFM-aware fault model and ATPG for intra-cell and inter-cell defects

A Sinha, S Pandey, A Singhal, A Sanyal… - … Test Conference (ITC …, 2017 - ieeexplore.ieee.org
Yield improvement, yield ramp, and defect screening have been major areas of concern for
the semiconductor industry as technology nodes have advanced. Much effort has been …

[HTML][HTML] Breast cancer detection using infrared spectral pathology from H&E stained tissue on glass slides

J Tang, D Kurfürstová, P Gardner - Clinical Spectroscopy, 2021 - Elsevier
Infrared spectral pathology has gained significant attention in the last few years, since it has
been demonstrated to be able to readily identify cancerous tissue in biopsy samples. The …

Diagnostic test point insertion and test compaction

I Pomeranz - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
Test points are inserted into a circuit to improve its testability or diagnosability. The
diagnosability goal may be to reduce the number of indistinguished fault pairs, increase the …

Front-end layout reflection for test chip design

Z Liu, P Fynan, RD Blanton - 2017 IEEE International Test …, 2017 - ieeexplore.ieee.org
Fast yield ramping in a new technology to meet aggressive time-to-market deadlines
requires a comprehensive design and fabrication methodology for silicon test structures that …

Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis

H Lim, H Yun, S Kang - … Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
Conventional diagnosis methods are performed at the library cell level, which identify only
defective cells. In reality, many defects affecting the inside of the cells cannot be identified …

Back-end layout reflection for test chip design

Z Liu, RD Blanton - 2018 IEEE 36th International Conference on …, 2018 - ieeexplore.ieee.org
At advanced technology nodes, complex interactions between layout features and the
process can lead to manufacturability issues that reduce yield. Due to the huge number of …

Multiple-defect diagnosis for logic characterization vehicles

B Niewenhuis, S Mittal… - 2017 22nd IEEE European …, 2017 - ieeexplore.ieee.org
Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has
emphasized the diagnosability properties of a specific class of regular circuits called …

[PDF][PDF] A Logic Test Chip for Optimal Test and Diagnosis.

B Niewenhuis - 2018 - kilthub.cmu.edu
The benefits of the continued progress in integrated circuit manufacturing have been
numerous, most notably in the explosion of computing power in devices ranging from cell …

A Repair-for-Diagnosis Methodology for Logic Circuits

CH Wu, SL Lin, KJ Lee… - IEEE Transactions on Very …, 2018 - ieeexplore.ieee.org
Fault diagnosis plays a major role in IC yield enhancement as it can help identify yield
limiting defects in fabricated devices. The information on such defects is used to guide …