Complementary-FET (CFET) standard cell synthesis framework for design and system technology co-optimization using SMT
With the relentless scaling of technology nodes, design technology co-optimization (DTCO)
for the conventional (Conv.) cell structure is starting to reach its limitations due to limited …
for the conventional (Conv.) cell structure is starting to reach its limitations due to limited …
Buried power rail integration with FinFETs for ultimate CMOS scaling
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node.
This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si …
This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si …
Buried power rails and nano-scale TSV: technology boosters for backside power delivery network and 3D heterogeneous integration
A Jourdain, M Stucchi, G Van der Plas… - 2022 IEEE 72nd …, 2022 - ieeexplore.ieee.org
Decoupling signal and power delivery routing to the transistors can be achieved by moving
the power wiring to the wafer backside while signal routing is kept in the traditional BEOL of …
the power wiring to the wafer backside while signal routing is kept in the traditional BEOL of …
Layout optimization of complementary FET 6T-SRAM cell based on a universal methodology using sensitivity with respect to parasitic-and-values
Y Luo, L Cao, Q Zhang, Y Cao, Z Zhang… - … on Electron Devices, 2022 - ieeexplore.ieee.org
Complementary FET (CFET) is a promising booster for further area reductions in static
random-access memory (SRAM) cells. However, the performance degrading by a series of …
random-access memory (SRAM) cells. However, the performance degrading by a series of …
Scaled FinFETs connected by using both wafer sides for routing via buried power rails
A Veloso, A Jourdain, D Radisic, R Chen… - … on Electron Devices, 2022 - ieeexplore.ieee.org
We report on scaled finFETs built with a novel routing scheme wherein devices are
connected via buried power rails (BPRs) from both wafer sides, with tight variability and …
connected via buried power rails (BPRs) from both wafer sides, with tight variability and …
Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and TSVs
MO Hossen, B Chava, G Van der Plas… - … on Electron Devices, 2019 - ieeexplore.ieee.org
In this article, a power delivery network (PDN) modeling framework for backside-PDN
configurations is presented. A backside-PDN configuration contains dense microthrough …
configurations is presented. A backside-PDN configuration contains dense microthrough …
Complementary FET (CFET) standard cell design for low parasitics and its impact on VLSI prediction at 3-nm process
E Park, T Song - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
Complementary field-effect transistor (CFET) is a future transistor type with a high potential
to be used beyond 3-nm technology nodes. Despite its high future value, studies related to …
to be used beyond 3-nm technology nodes. Despite its high future value, studies related to …
Probe3. 0: A systematic framework for design-technology pathfinding with improved design enablement
We propose a systematic framework to conduct design-technology pathfinding for power,
performance, area, and cost (PPAC) in advanced nodes. Our goal is to provide a …
performance, area, and cost (PPAC) in advanced nodes. Our goal is to provide a …
A holistic evaluation of buried power rails and back-side power for sub-5 nm technology nodes
Buried power rail (BPR) and back-side power delivery grid have been proposed as solutions
to scaling challenges that arise beyond the 5-nm technology node, mainly to lower IR drop …
to scaling challenges that arise beyond the 5-nm technology node, mainly to lower IR drop …
A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT
As the technology node is evolving, standard cell (SDC) design scaling is obstructed by
design constraints such as limited routing resources, lateral PN separation, and …
design constraints such as limited routing resources, lateral PN separation, and …