Druto: Upper-bounding silent data corruption vulnerability in gpu applications

MH Rahman, S Di, S Guo, X Lu, G Li… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
Due to the increasing scale of high-performance computing (HPC) systems, transient
hardware faults have become a major reliability concern. Consequently, Silent Data …

Software-based Control-Flow Error Detection with Hardware Performance Counters in ARM Processors

HAH Ahmad, Y Sedaghat - 2022 CPSSI 4th International …, 2022 - ieeexplore.ieee.org
The recent trend in processor manufacturing technologies has significantly increased the
susceptibility of safety-critical systems against soft errors in harsh environments. Such errors …

Layout based radiation hardening techniques against single-event transient

B Liang, D Luo, Q Sun, W Chen - Microelectronics Reliability, 2022 - Elsevier
The single-event transient (SET) is regarded as one of the critical reliability issues for the soft
errors in modern circuit designs, especially at the advanced technology node. To improve …

FERNANDO: A software transient fault tolerance approach for embedded systems based on redundant multi-threading

H Wu, R Guo, Y Hu - IEEE Access, 2021 - ieeexplore.ieee.org
As semiconductor technology scales, modern microprocessors are more vulnerable to
transient faults. Software-level fault tolerance schemes are promising because they can …

Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches

J Mach, L Kohútka, P Čičak - 2024 27th Euromicro Conference …, 2024 - ieeexplore.ieee.org
Mission/safety-critical applications rely on the dependability of their semiconductor control
systems. The lockstepping is state-of-the-art when it comes to their protection. This paper …

Lockstep Vs Microarchitecture: A Comparison

J Mach, L Kohútka, P Čičák - 2024 IEEE 37th International …, 2024 - ieeexplore.ieee.org
Safety/mission-critical applications require high dependability of the control systems. Their
state-of-the-art protection approach is a system-level lockstep. This paper compares the …

SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment

KL Lu, YY Chen - Journal of Circuits, Systems and Computers, 2021 - World Scientific
We propose a safety-oriented design process for IP-based safety-critical system-on-chip
(SoC). The proposed safety process can facilitate the measurement of the robustness based …

[PDF][PDF] Comparing 6T & 13T SRAM Bit Cell & using FinFET to construct the superior in 22nm Scale for usage in Spacecrafts

M Singh, S Sen, A Dasgupta, A Das - 2021 - ceur-ws.org
The soft error in SRAM is generated as the single ionizing particle strikes a sensitive node,
which gives rise to Single Event Upsets (SEU)[1]. Here in this paper we design and examine …