A variation-aware hold time fixing methodology for single flux quantum logic circuits

Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic

S Razmkhah, RS Aviles, M Li, S Gupta… - … , Automation & Test …, 2024 - ieeexplore.ieee.org
Positioned as a highly promising post-CMOS computing technology, superconductor
electronics (SCE) offer the potential for unparalleled performance and energy efficiency …
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[PDF] arxiv.org

Delay Balancing with Clock-Follow-Data: Optimizing Area Delay Trade-offs for Robust Rapid Single Flux Quantum Circuits

RS Aviles, PA Beerel - arXiv preprint arXiv:2409.04944, 2024 - arxiv.org
This paper proposes an algorithm for synthesis of clock-follow-data designs that provides
robustness against timing violations for RSFQ circuits while maintaining high performance …
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