Silicon nanowire heterostructures for advanced energy and environmental applications: a review

R Ghosh, PK Giri - Nanotechnology, 2016 - iopscience.iop.org
Semiconductor nanowires (NWs), in particular Si NWs, have attracted much attention in the
last decade for their unique electronic properties and potential applications in several …

[HTML][HTML] Ge nanowire photodetector with high photoconductive gain epitaxially integrated on Si substrate

U Otuonye, HW Kim, WD Lu - Applied Physics Letters, 2017 - pubs.aip.org
Efficient nanoscale photodetectors are desirable for future applications such as on-chip
optical interconnect systems. High density integration, ideally at the transistor level, requires …

Vertical Ge/Si core/shell nanowire junctionless transistor

L Chen, F Cai, U Otuonye, WD Lu - Nano Letters, 2016 - ACS Publications
Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si
core/shell nanowires epitaxially grown and integrated on a⟨ 111⟩ Si substrate were …

Implementing logic functions using independently-controlled gate in double-gate tunnel FETs: investigation and analysis

S Garg, S Saurabh - IEEE Access, 2019 - ieeexplore.ieee.org
Recently, a compact realization of logic gates using double-gate tunnel field effect
transistors (DGTFETs) with independently-controlled gate has been proposed. The key …

A halide perovskite thin film diode with modulated depletion layers for artificial synapse

WM Zhong, XG Tang, LL Bai, JY Chen, HF Dong… - Journal of Alloys and …, 2023 - Elsevier
Artificial synapse is basic electronic components used to prepare neuromorphic hardware
with integrated storage and computing, high speed and low energy consumption. This work …

[PDF][PDF] Sub‐50 nm Channel Vertical Field‐Effect Transistors using Conventional Ink‐Jet Printing

TT Baby, M Rommel, F von Seggern… - Advanced …, 2017 - scholar.archive.org
Department of Materials Engineering Indian Institute of Science Bangalore 560012, India
have long-time outperformed amorphous silicon. However, the resolution of the present …

Semiconductor nanowire growth and integration

L Chen, W Lu, CM Lieber - 2014 - books.rsc.org
To date, numerous studies have been carried out to explore nanowires as new building
blocks in electronics, 1–11 photonics, 12–24 solar-cells, 25–29 batteries, 30–34 …

Realization of high-speed logic functions using heterojunction vertical TFET

V Ambekar, M Panchore - Applied Physics A, 2023 - Springer
In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium
as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A …

Controlling the interface areas of organic/inorganic semiconductor heterojunction nanowires for high-performance diodes

Z Xue, H Yang, J Gao, J Li, Y Chen, Z Jia… - … applied materials & …, 2016 - ACS Publications
A new method of in situ electrically induced self-assembly technology combined with
electrochemical deposition has been developed for the controllable preparation of …

Double gate symmetric tunnel FET: investigation and analysis

S Ramaswamy, MJ Kumar - IET Circuits, Devices & Systems, 2017 - Wiley Online Library
In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF‐state
current and subthreshold swing (SS) are significantly high for the double gate Ge …