A bus system comprising a master connected to one or more slave devices via a bus is
disclosed. The bus system is able to effectively communicate control information during a …

2006-08-02 Assigned to METARAM, INC. reassignment METARAM, INC. ASSIGNMENT OF
ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WEBER …

(57) ABSTRACT A precision timing generator includes a combiner that pro vides a timing
Signal by combining a coarse timing Signal and a fine timing Signal derived from a phase …

A signaling system includes a signaling path, a master device coupled to the signaling path,
a slave device coupled to the signaling path, and a clock generator. The slave device …

First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
23669064&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

(57) ABSTRACT A bus capture circuit captures digital Signals applied on respective lines of
a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock …

An integrated circuit device includes a receiver, a register and a clock circuit. The receiver
Samples data from an external signal line in response to an internal clock signal. The …

US6304623B1 - Precision timing generator system and method - Google Patents
US6304623B1 - Precision timing generator system and method - Google Patents Precision …

FOREIGN PATENT DOCUMENTS each phase command Signal. The control circuit
generates a final phase command Signal from the Stored results signals and applies each …

A method and circuit adaptively adjust respective timing offsets of digital signals relative to a
clock output along with the digital signals to enable a latch receiving the digital signals to …