(57) One embodiment of the present invention relates to a digital phase locked loop
(ADPLL) configured to generate a plural ity of time-aligned output clock signals having …

(TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase
error detector. The deter ministic nature of the phase error during frequency/phase lock is …

A system is provided for processing a communication signal including a baseband
amplitude component and a baseband phase component. The system includes an …

A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to
store control input for the oscillator. The PLL is operable in a calibration mode in which the …

Radio transmitters using the polar scheme utilize a CO-ORDInate Calculator (CORDIC) to
transform the often interpolated baseband data in Cartesian format to its polar equivalent …

In recent years, there has been a rapid increase in demand for delivery of real-time
applications and services in com puter networks, including Pseudo-Wire Emulation (PWE) …

In one embodiment, a method comprising during a first calibration instance, converting at a
first transconductance stage a first output voltage from a power amplifier of a transceiver to a …

A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an
oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase …

The present application claims priority to US Patent Application Ser. No. 61/898,064 filed on
Oct. 31, 2013 and entitled “MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED …

A PAPR determining device includes a detecting unit and a PAPR determining unit. The
detecting unit detects a predetermined value's changes, which is a cause of changes in a …