Efficiently Synthesizing a Complete Set of Unique Instruction Selection Rewrite Rules Using SMT

R Daly - 2024 - search.proquest.com
With the ever-evolving landscape of computer architecture, we are witnessing an influx of
novel intermediate representations (IRs) and instruction set architectures (ISAs). These …

Taming an authoritative Armv8 ISA specification: L3 validation and CakeML compiler verification

H Kanabar, ACJ Fox, MO Myreen - 13th International Conference …, 2022 - drops.dagstuhl.de
Abstract Machine-readable specifications for the Armv8 instruction set architecture have
become publicly available as part of Arm's release processes, providing an official and …

Cornucopia: A framework for feedback guided generation of binaries

V Singhal, AA Pillai, C Saumya, M Kulkarni… - Proceedings of the 37th …, 2022 - dl.acm.org
Binary analysis is an important capability required for many security and software
engineering applications. Consequently, there are many binary analysis techniques and …

[PDF][PDF] GRIFT: A richly-typed, deeply-embedded RISC-V semantics written in Haskell

B Selfridge - Workshop on Instruction Set Architecture Specification …, 2019 - cl.cam.ac.uk
We introduce the Galois RISC-V Formal Tools (GRIFT)[1], a formal specification of the RISC-
V instruction set architecture written in the Haskell programming language. It consists of a …

[PDF][PDF] End-to-end formal verification of a risc-v processor extended with capability pointers

D Gao, T Melham - 2021 Formal Methods in Computer Aided …, 2021 - library.oapen.org
Capability Hardware Enhanced RISC Instructions (CHERI) extend conventional ISAs with
capabilities that can enable fine-grained memory protection and scalable software …

On Hardware Verification In An Open Source Context

B Marshall - Workshop on Open Source Design …, 2019 - research-information.bris.ac.uk
The last few decades have seen the complexity of commercial hardware designs increase
by multiple orders of magnitude. This has driven corresponding increases in commercial tool …

ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures

A Ramdas, M Giardino, R Shi, A Turowski… - arXiv preprint arXiv …, 2022 - arxiv.org
Unlike other accelerators, FPGAs are capable of supporting cache coherency, thereby
turning them into a more powerful architectural option than just a peripheral accelerator …

Defining interfaces between hardware and software: Quality and performance

AD Reid - 2019 - theses.gla.ac.uk
One of the most important interfaces in a computer system is the interface between hardware
and software. This interface is the contract between the hardware designer and the …

Specifying verified x86 software from scratch

M Carneiro - arXiv preprint arXiv:1907.01283, 2019 - arxiv.org
We present a simple framework for specifying and proving facts about the input/output
behavior of ELF binary files on the x86-64 architecture. A strong emphasis has been placed …

Verified compilation of a purely functional language to a realistic machine semantics

H Kanabar - 2024 - kar.kent.ac.uk
Formal verification of a compiler offers the ultimate understanding of the behaviour of
compiled code: a mathematical proof relates the semantics of each output program to that of …