Physically unclonable functions using two-level finite state machine
V Vijay, K Chaitanya, CS Pittala… - Journal of VLSI …, 2022 - vlsijournal.com
The usage of physically unclonable functions is for authentications, identification
applications, signature generation, IC metering, and cryptographic key generation …
applications, signature generation, IC metering, and cryptographic key generation …
Smart cart shopping system with an RFID interface for human assistance
RR Vallabhuni, S Lakshmanachari… - 2020 3rd …, 2020 - ieeexplore.ieee.org
As the Internet of Things (IoT) is relying on the exchange of information, this research work
progress through analyzing the radio frequency identification, which is an emerging …
progress through analyzing the radio frequency identification, which is an emerging …
6Transistor SRAM cell designed using 18nm FinFET technology
RR Vallabhuni, P Shruthi, G Kavya… - 2020 3rd International …, 2020 - ieeexplore.ieee.org
The electronics devices are facing a foremost drawback of standby leakage, which will
severely impact the electronics industry from the past few decades. As well as the need for …
severely impact the electronics industry from the past few decades. As well as the need for …
Design of unbalanced ternary logic gates and arithmetic circuits
V Vijay, CS Pittala, KC Koteshwaramma… - Journal of VLSI …, 2022 - vlsijournal.com
The design of ternary Logic gates–Ternary NAND, Ternary NOR and Standard Ternary
Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems …
Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems …
Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology
CS Pittala, M Lavanya, V Vijay, Y Reddy… - 2021 Devices for …, 2021 - ieeexplore.ieee.org
VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in
electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder …
electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder …
Fake currency recognition system using edge detection
In this paper, we propose a system for currency recognition system and the detection of fake
Indian currency banknotes using image processing techniques. It is hard for people to …
Indian currency banknotes using image processing techniques. It is hard for people to …
Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer
J Sravana, KS Indrani, M Saranya, PS Kiran… - Journal of VLSI …, 2022 - vlsijournal.com
This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic
standards, which includes old sutras. In this paper, current and proposed model are …
standards, which includes old sutras. In this paper, current and proposed model are …
Implementation of Spurious Power Suppression based Radix-4 Booth Multiplier using Parallel Prefix Adders
J Sravana, SKH Bindhu, K Sharvani… - … on Recent Trends in …, 2022 - ieeexplore.ieee.org
In VLSI, for performing multiplication, we use a* b. We use the booth multiplication
mechanism rather than the standard conventional method to improve the speed since it …
mechanism rather than the standard conventional method to improve the speed since it …
High-Performance IIR Filter Implementation Using FPGA
V Vijay, VRS Rao, K Chaitanya… - … on Recent Trends in …, 2022 - ieeexplore.ieee.org
This document investigation is performed on improved implementation of an Infinite Impulse
Response (IIR) filter which can utilized practically. There are many other proposed models …
Response (IIR) filter which can utilized practically. There are many other proposed models …
A hybrid PAPR reduction technique in OFDM systems
VS Nagaraju, R Anusha… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
In a communication system, OFDM is the best technique for high speed transfer amplification
in a communication network. The principal downside in the OFDM system was PAPR (Peak …
in a communication network. The principal downside in the OFDM system was PAPR (Peak …