Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design
Sum of absolute differences (SAD) calculation is one of the most time-consuming operations
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
Configurable memory with a multilevel shared structure enabling in-memory computing
Frequent to-and-from data transfers in the von Neumann architecture limit the overall
throughput. One of the promising approaches used to overcome von Neumann bottleneck is …
throughput. One of the promising approaches used to overcome von Neumann bottleneck is …
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding
The sum of absolute difference (SAD) calculation is one of the most computing-intensive
operations in video encoders compatible with recent standards, such as high-efficiency …
operations in video encoders compatible with recent standards, such as high-efficiency …
SAD or SATD? how the distortion metric impacts a Fractional Motion Estimation VLSI architecture
I Seidel, V Rodrigues Filho, M Grellert… - 2021 IEEE 23rd …, 2021 - ieeexplore.ieee.org
Video coding systems have to deal with a number of tradeoffs. The decision of adopting a
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation
Integer motion estimation performs a pivotal role in achieving video compression by
exploiting the temporal redundancy of video sequences. However, the motion estimation's …
exploiting the temporal redundancy of video sequences. However, the motion estimation's …
Low power sum of absolute differences architecture using novel hybrid adder
R Ferreira, B Silveira, MB Fonseca… - 2017 IEEE 8th Latin …, 2017 - ieeexplore.ieee.org
Sum of Absolute Differences (SAD) is an intensive time-consuming operation of state-of-art
video encoders. It is used as a block matching metric inside Motion Estimation (ME) and also …
video encoders. It is used as a block matching metric inside Motion Estimation (ME) and also …
[PDF][PDF] Comparison of 90nm and 65nm Logic Synthesis of a SAD Configurable VLSI Architecture
This paper evaluates the impact of the technology node on the area, performance and
power consumption of a configurable VLSI architecture for Sum of Absolutes Differences …
power consumption of a configurable VLSI architecture for Sum of Absolutes Differences …