A review of various control strategies based on space vector pulse width modulation for the voltage source inverter
E Nandhini, A Sivaprakasam - IETE Journal of Research, 2022 - Taylor & Francis
Voltage source inverters are the most preferred in a variety of medium and high power
applications. The control of inverter output voltage gives desirable outputs in drives and …
applications. The control of inverter output voltage gives desirable outputs in drives and …
Integrated modulation of dual-parallel three-level inverters with reduced common mode voltage and circulating current
W Li, X Zhang, F Zhang, S Zhang, Z Fu… - … on Power Electronics, 2021 - ieeexplore.ieee.org
Many reduced common mode voltage (CMV) modulation methods have been proposed for
three-level inverters. However, most of them suffer from large current distortion because only …
three-level inverters. However, most of them suffer from large current distortion because only …
Optimal discontinuous space vector PWM for zero-sequence-circulating current reduction in two paralleled three-phase two-level converter
Z Zeng, Z Li, SM Goetz - IEEE Transactions on Industrial …, 2020 - ieeexplore.ieee.org
This article proposes an optimal discontinuous pulsewidth modulation (ODPWM) strategy to
reduce the zero-sequence circulating current (ZSCC) for paralleled three-phase two-level …
reduce the zero-sequence circulating current (ZSCC) for paralleled three-phase two-level …
A five-level space vector modulation scheme for parallel operated three-level inverters with reduced line current distortion
W Li, X Zhang, Y Zhuang, G Zhang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Parallel operation of voltage source inverters is useful to achieve larger power capacity and
improve the system reliability, which has become the trend of power system design …
improve the system reliability, which has become the trend of power system design …
Line current ripple minimization PWM strategy with reduced zero-sequence circulating current for two parallel interleaved three-phase converters
Z Zeng, Z Li, SM Goetz - IEEE Transactions on Power …, 2019 - ieeexplore.ieee.org
This article proposes a line-current ripple minimization pulsewidth modulation strategy with
reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level …
reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level …
Reduction of zero-sequence and differential-mode circulating currents and common-mode voltage in parallel PWM converters
This article aims to present a reduction strategy for circulating current and common-mode
voltage in parallel pulsewidth modulated (PWM) converters. As the common-mode voltage …
voltage in parallel pulsewidth modulated (PWM) converters. As the common-mode voltage …
Model predictive current control based on virtual voltage vector method for parallel three-level inverters
T Jin, Y Huang, Y Lin… - IEEE Journal of Emerging …, 2021 - ieeexplore.ieee.org
The parallel three-level neutral-point clamp (3L-NPC) inverters are widely solicited today to
satisfy the higher power demand by using low-rated switching devices in industrial …
satisfy the higher power demand by using low-rated switching devices in industrial …
A high performance interleaved discontinuous PWM strategy for two paralleled three-phase inverter
Z Zeng, Z Li, SM Goetz - IEEE Transactions on Power …, 2020 - ieeexplore.ieee.org
This article aims to obtain the optimal combination of the switching loss, maximum zero-
sequence circulating current (ZSCC), and line current ripple, which benefits most of the …
sequence circulating current (ZSCC), and line current ripple, which benefits most of the …
Implementation of five-level DPWM on parallel three-level inverters to reduce common-mode voltage and AC current ripples
W Li, X Zhang, Z Zhao, G Zhang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Conventional reduced common-mode voltage discontinuous pulsewidth modulation method
for a three-level inverter can reduce the common-mode voltage and switching transitions …
for a three-level inverter can reduce the common-mode voltage and switching transitions …
A modified DPWM method with minimal line current ripple and zero-sequence circulating current for two parallel interleaved 2L-VSIs
S He, Y Wang, B Liu - IEEE Transactions on Industrial …, 2021 - ieeexplore.ieee.org
High-performance comprehensive optimization of line current ripple, zero-sequence
circulating current (ZSCC), and switching losses is a challenge for parallel interleaved …
circulating current (ZSCC), and switching losses is a challenge for parallel interleaved …