Approximate computing and the quest for computing efficiency

S Venkataramani, ST Chakradhar, K Roy… - Proceedings of the …, 2015 - dl.acm.org
Diminishing benefits from technology scaling have pushed designers to look for new
sources of computing efficiency. Multicores and heterogeneous accelerator-based …

Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

S Ghosh, K Roy - Proceedings of the IEEE, 2010 - ieeexplore.ieee.org
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

Computing approximately, and efficiently

S Venkataramani, ST Chakradhar… - … , Automation & Test …, 2015 - ieeexplore.ieee.org
Recent years have witnessed significant interest in the area of approximate computing.
Much of this interest stems from the quest for new sources of computing efficiency in the face …

DTA-PUF: Dynamic timing-aware physical unclonable function for resource-constrained devices

I Tsiokanos, J Miskelly, C Gu, M O'neill… - ACM Journal on …, 2021 - dl.acm.org
In recent years, physical unclonable functions (PUFs) have gained a lot of attention as
mechanisms for hardware-rooted device authentication. While the majority of the previously …

Process-variation resilient and voltage-scalable DCT architecture for robust low-power computing

G Karakonstantis, N Banerjee… - IEEE Transactions on Very …, 2009 - ieeexplore.ieee.org
In this paper, we present a novel discrete cosine transform (DCT) architecture that allows
aggressive voltage scaling for low-power dissipation, even under process parameter …

Exploring the fidelity-efficiency design space using imprecise arithmetic

J Huang, J Lach - 16th Asia and South Pacific Design …, 2011 - ieeexplore.ieee.org
Recently many imprecise circuit design techniques have been proposed for implementation
of error-tolerant applications, such as multimedia and communications. These algorithms do …

Microarchitecture-aware timing error prediction via deep neural networks

S Tompazi, G Karakonstantis - … on On-Line Testing and Robust …, 2023 - ieeexplore.ieee.org
Nanometer circuits are becoming increasingly prone to timing errors due to worsening
parametric variations and operation close to voltage and frequency limits. Such errors …

Minimum-energy operation via error resiliency

RA Abdallah, NR Shanbhag - IEEE Embedded Systems Letters, 2010 - ieeexplore.ieee.org
Error resiliency has demonstrated significant robustness and energy benefits in
superthreshold performance-constrained applications (Shanbhag, Proc. Des. Autom. Conf …

HERQULES: System level cross-layer design exploration for efficient energy-quality trade-offs

G Karakonstantis, G Panagopoulos, K Roy - Proceedings of the 16th …, 2010 - dl.acm.org
In this paper, we present a unique cross-layer design framework that allows systematic
exploration of the energy-delay-quality trade-offs at the algorithm, architecture and circuit …

A cross-layer reliability design methodology for efficient, dependable wireless receivers

C Gimmler-Dumont, N Wehn - ACM Transactions on Embedded …, 2014 - dl.acm.org
Continued progressive downscaling of CMOS technologies threatens the reliability of chips
for future embedded systems. We developed a novel design methodology for dependable …