The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware
subsystems to implement a system. A wide range of MPSoC architectures have been …

We present a survey of the state-of-the-art techniques used in performing data and memory-
related optimizations in embedded systems. The optimizations are targeted directly or …

Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed
for different groups in the embedded systems-on-chip arena. First, it is designed for …

As the gap between memory and processor speeds continues to widen, cache efficiency is
an increasingly important component of processor per $ ormance. Compiler techniques …

Poor data layout in memory may generate weak data locality and poor performance. Code
transformations such as loop blocking or interchanging and array padding have addressed …

In this paper, we focus on low-power design techniques for high-performance processors at
the architectural and compiler levels. We focus mainly on developing methods for reducing …

In an embedded system, it is common to have several memory areas with different
properties, such as access time and size. An access to a specific memory area is usually …

High-Performance Embedded Computing, Second Edition, combines leading-edge
research with practical guidance in a variety of embedded computing topics, including real …

To improve memory bandwidth and power consumption in video applications, a new
memory-interface architecture is proposed. The architecture adopts an array address …

Embedded processor-based systems allow for the tailoring of the on-chip memory
architecture based on application specific requirements. We present an analytical strategy …