Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache

K Korgaonkar, I Bhati, H Liu, J Gaur… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
Increasing the capacity of the Last Level Cache (LLC) can help scale the memory wall. Due
to prohibitive area and leakage power, however, growing conventional SRAM LLC already …

Extreme value theory for estimating task execution time bounds: A careful look

G Lima, D Dias, E Barros - 2016 28th Euromicro Conference on …, 2016 - ieeexplore.ieee.org
Extreme Value Theory (EVT) is a powerful statistical framework for estimating maximum
values of random variables and has recently been applied for deriving probabilistic bounds …

An extensible framework for multicore response time analysis

RI Davis, S Altmeyer, LS Indrusiak, C Maiza, V Nelis… - Real-Time …, 2018 - Springer
In this paper, we introduce a multicore response time analysis (MRTA) framework, which
decouples response time analysis from a reliance on context-independent WCET values …

Mixed criticality systems with varying context switch costs

RI Davis, S Altmeyer, A Burns - 2018 IEEE Real-Time and …, 2018 - ieeexplore.ieee.org
In mixed criticality systems, it is vital to ensure that there is sufficient separation between
tasks of LO-and HI-criticality applications, so that the behavior or mis-behavior of the former …

Inter-task cache interference aware partitioned real-time scheduling

Z Guo, K Yang, F Yao, A Awad - Proceedings of the 35th annual ACM …, 2020 - dl.acm.org
With the increasing number of cores in processors, shared resources like caches are
interfering task execution behaviours more heavily and often render global scheduling …

Minimizing cache usage with fixed-priority and earliest deadline first scheduling

B Sun, T Kloda, SA Garcia, G Gracioli, M Caccamo - Real-Time Systems, 2024 - Springer
Cache partitioning is a technique to reduce interference among tasks running on the
processors with shared caches. To make this technique effective, cache segments should be …

[PDF][PDF] Implementation of memory centric scheduling for COTS multi-core real-time systems

JM Rivas, J Goossens, X Poczekajlo… - … Conference on Real …, 2019 - drops.dagstuhl.de
The demands for high performance computing with a low cost and low power consumption
are driving a transition towards multi-core processors in many consumer and industrial …

On the trade-offs between generalization and specialization in real-time systems

G von der Brüggen, A Burns, JJ Chen… - 2022 IEEE 28th …, 2022 - ieeexplore.ieee.org
While academia favours general research that is applicable to a large class of systems, this
paper highlights the necessity of research into specific scenarios and aims to increase its …

A framework for multi-core schedulability analysis accounting for resource stress and sensitivity

RI Davis, D Griffin, I Bate - Real-Time Systems, 2022 - Springer
Timing verification of multi-core systems is complicated by contention for shared hardware
resources between co-running tasks on different cores. This paper introduces the Multi-core …

Integrated analysis of cache related preemption delays and cache persistence reload overheads

SA Rashid, G Nelissen, S Altmeyer… - 2017 IEEE Real …, 2017 - ieeexplore.ieee.org
Schedulability analysis for tasks running on micro-processors with cache memory is
incomplete without a treatment of Cache Related Preemption Delays (CRPD) and Cache …