Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache
Increasing the capacity of the Last Level Cache (LLC) can help scale the memory wall. Due
to prohibitive area and leakage power, however, growing conventional SRAM LLC already …
to prohibitive area and leakage power, however, growing conventional SRAM LLC already …
Extreme value theory for estimating task execution time bounds: A careful look
Extreme Value Theory (EVT) is a powerful statistical framework for estimating maximum
values of random variables and has recently been applied for deriving probabilistic bounds …
values of random variables and has recently been applied for deriving probabilistic bounds …
An extensible framework for multicore response time analysis
In this paper, we introduce a multicore response time analysis (MRTA) framework, which
decouples response time analysis from a reliance on context-independent WCET values …
decouples response time analysis from a reliance on context-independent WCET values …
Mixed criticality systems with varying context switch costs
In mixed criticality systems, it is vital to ensure that there is sufficient separation between
tasks of LO-and HI-criticality applications, so that the behavior or mis-behavior of the former …
tasks of LO-and HI-criticality applications, so that the behavior or mis-behavior of the former …
Inter-task cache interference aware partitioned real-time scheduling
With the increasing number of cores in processors, shared resources like caches are
interfering task execution behaviours more heavily and often render global scheduling …
interfering task execution behaviours more heavily and often render global scheduling …
Minimizing cache usage with fixed-priority and earliest deadline first scheduling
Cache partitioning is a technique to reduce interference among tasks running on the
processors with shared caches. To make this technique effective, cache segments should be …
processors with shared caches. To make this technique effective, cache segments should be …
[PDF][PDF] Implementation of memory centric scheduling for COTS multi-core real-time systems
JM Rivas, J Goossens, X Poczekajlo… - … Conference on Real …, 2019 - drops.dagstuhl.de
The demands for high performance computing with a low cost and low power consumption
are driving a transition towards multi-core processors in many consumer and industrial …
are driving a transition towards multi-core processors in many consumer and industrial …
On the trade-offs between generalization and specialization in real-time systems
While academia favours general research that is applicable to a large class of systems, this
paper highlights the necessity of research into specific scenarios and aims to increase its …
paper highlights the necessity of research into specific scenarios and aims to increase its …
A framework for multi-core schedulability analysis accounting for resource stress and sensitivity
Timing verification of multi-core systems is complicated by contention for shared hardware
resources between co-running tasks on different cores. This paper introduces the Multi-core …
resources between co-running tasks on different cores. This paper introduces the Multi-core …
Integrated analysis of cache related preemption delays and cache persistence reload overheads
Schedulability analysis for tasks running on micro-processors with cache memory is
incomplete without a treatment of Cache Related Preemption Delays (CRPD) and Cache …
incomplete without a treatment of Cache Related Preemption Delays (CRPD) and Cache …