A new circuit-level technique for leakage and short-circuit power reduction of static logic gates in 22-nm CMOS technology
M Moradinezhad Maryan, M Amini-Valashani… - Circuits, Systems, and …, 2021 - Springer
The leakage power, aka static power, increases in deep-submicron technologies due to
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories
K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Static or leakage power is the dominating component of total power dissipation in deep
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
Proposed design of 1 KB memory array structure for cache memories
K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Technology scaling facilitates to meet ever increasing demands for a portable and battery
operated systems, at the same time causes diminution of length of the channel, gate oxide …
operated systems, at the same time causes diminution of length of the channel, gate oxide …
The sub-threshold leakage reduction techniques in CMOS circuits
Minimizing the leakage power has become one of the major concerns in low-voltage, low-
power and high performance applications in VLSI involving CMOS circuits. The first part of …
power and high performance applications in VLSI involving CMOS circuits. The first part of …
Fast and high-performing 1-bit full adder circuit based on input switching activity patterns and gate diffusion input technique
I Hussain, S Chaudhury - Circuits, Systems, and Signal Processing, 2021 - Springer
For computational arithmetic, a full adder is the primary logic units in VLSI applications. A
new full adder circuit design has been presented in this article which is based on input …
new full adder circuit design has been presented in this article which is based on input …
Performance Analysis of 6T and 11T SRAM Cell Topologies at 45nm Era
D Mittal - 2022 International Conference for Advancement in …, 2022 - ieeexplore.ieee.org
The cadence virtuoso tool was utilized in this study to simulate a 45-nm innovation GPDK
using the cadence virtuoso tool. Power consumption is a significant issue for electronic …
using the cadence virtuoso tool. Power consumption is a significant issue for electronic …
INDIDO: A novel low-power approach for domino logic circuits
Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by
leakage power dissipation. This is due to an increase in short channel effects in the scaled …
leakage power dissipation. This is due to an increase in short channel effects in the scaled …
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits
H Mohammadian, MB Tavakolib, F Setoudeh, A Horri - Integration, 2021 - Elsevier
By the reduction in the size of transistors and the development of submicron technology, as
well as the construction of more integrated circuits on chips, leakage power has become one …
well as the construction of more integrated circuits on chips, leakage power has become one …
SRAM Cell Leakage Reduction Methodologies for Low Leakage Cache Memories
D Mittal - 2023 14th International Conference on Computing …, 2023 - ieeexplore.ieee.org
Static memory cells (SRAMs) are a kind that are used in many different electrical systems. It
uses less energy, works more rapidly than other memory cells, and doesn't need to be …
uses less energy, works more rapidly than other memory cells, and doesn't need to be …
An Electronically Tunable Low Power Low Pass Filter Employing Capacitor Multiplier for Biomedical Applications
D Özenli, E Alaybeyoğlu - Erzincan University Journal of Science …, 2022 - dergipark.org.tr
In this work, a novel 0.9 nW low pass filter is proposed using 0.18 µm TSMC technology in
Cadence environment to reject unwanted signals of biomedical applications. Active RC filter …
Cadence environment to reject unwanted signals of biomedical applications. Active RC filter …