Uniformity tuning of variable-height features formed in trenches
R Xie - US Patent 10,332,963, 2019 - Google Patents
Methods of forming a structure for a field-effect transistor and related structures. A trench is
formed in one or more semiconductor layers, and forming first and second sacrifi cial …
formed in one or more semiconductor layers, and forming first and second sacrifi cial …
High density nanosheet diodes
K Cheng, J Li, G Wang, Q Zhang - US Patent 9,842,835, 2017 - Google Patents
Embodiments are directed to a method for forming a semi conductor structure by depositing
a stack of alternating layers of two materials over a substrate and defining field effect …
a stack of alternating layers of two materials over a substrate and defining field effect …
Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET
UK Das, TK Bhattacharyya - IEEE transactions on electron …, 2020 - ieeexplore.ieee.org
The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped
FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To …
FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To …
Nanosheet channel-to-source and drain isolation
MA Bergendahl, K Cheng, FL Lie, ER Miller… - US Patent …, 2017 - Google Patents
A method and structures are used to fabricate a nanosheet semiconductor device.
Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and …
Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and …
Extension region for a semiconductor device
(57) ABSTRACT A method of forming a semiconductor device having a channel and a
source-drain coupled to the channel. The method includes etching a channel region such …
source-drain coupled to the channel. The method includes etching a channel region such …
Buffer regions for blocking unwanted diffusion in nanosheet transistors
Embodiments of the invention are directed to a method of fabricating a semiconductor
device. A non-limiting example of the method includes performing fabrication operations to …
device. A non-limiting example of the method includes performing fabrication operations to …
Air gap spacer between contact and gate region
Unfilled gaps are provided as spacers between gate stacks and electrically conductive
source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers …
source/drain contacts to reduce parasitic capacitance in CMOS structures. Sidewall spacers …
Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same
MS Rodder, JG Hong - US Patent 10,008,583, 2018 - Google Patents
A method of manufacturing a gate-all-around (GAA) nanosheet (NS) field effect transistor
(FET) includes forming a stack on a substrate. The stack includes an alternating …
(FET) includes forming a stack on a substrate. The stack includes an alternating …
Dual channel structures with multiple threshold voltages
R Bao, MA Guillorn, V Narayanan - US Patent 9,997,519, 2018 - Google Patents
(57) ABSTRACT A method of forming a semiconductor structure includes depositing a first
work function metal layer in nanosheet channel stacks for first and second CMOS structure …
work function metal layer in nanosheet channel stacks for first and second CMOS structure …
Series resistance reduction in vertically stacked silicon nanowire transistors
CC Yeh, X Cai, Q Liu, R Xie - US Patent 10,134,840, 2018 - Google Patents
Embodiments are directed to a method of fabricating a portion of a nanowire field effect
transistor (FET). The method includes forming a sacrificial layer and a nanowire layer …
transistor (FET). The method includes forming a sacrificial layer and a nanowire layer …