A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection …

W Deng, D Yang, T Ueno, T Siriburanon… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …

[图书][B] Sinusoidal oscillators and waveform generators using modern electronic circuit building blocks

R Senani, DR Bhaskar, VK Singh, RK Sharma - 2016 - Springer
Sinusoidal oscillators and waveform generators have numerous applications in electronics,
instrumentation, measurement, communications, control systems, and signal processing …

A 2.5–5.75-GHz ring-based injection-locked clock multiplier with background-calibrated reference frequency doubler

A Elkholy, D Coombs, RK Nandwana… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is
presented. It employs a background-calibrated reference frequency doubler to increase the …

A 1.6-to-3.0-GHz Fractional- MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

A Santiccioli, M Mercandelli, AL Lacaita… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs),
which differs from the more typical phase-locked loop one, and identifies a design …

A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop

S Levantino, G Marucci, G Marzin… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
Although multiplying delay-locked loops allow clock frequency multiplication with very low
phase noise and jitter, their application has been so far limited to integer-N multiplication …

A charge-sharing locking technique with a general phase noise theory of injection locking

Y Hu, X Chen, T Siriburanon, J Du… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …

A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique

Y Lee, T Seong, S Yoo, J Choi - IEEE Journal of Solid-State …, 2017 - ieeexplore.ieee.org
A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based
switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability …

[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

S Yang, J Yin, Y Liu, Z Zhu, R Bao, J Lin, H Li, Q Li… - Chip, 2023 - Elsevier
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

An injection-locked ring-oscillator-based fractional-N digital PLL supporting BLE frequency modulation

Y He, J van den Heuvel, P Mateman… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents an injection-locked (IL) ring-oscillator-based fractional-digital phase
locked loop (DPLL) supporting Bluetooth low energy (BLE) frequency modulation with an …

Time-variant modeling and analysis of multiplying delay-locked loops

A Santiccioli, C Samori, AL Lacaita… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper presents a novel time-variant model of multiplying delay-locked loops. A simple
feed-forward model of the multiplexed ring oscillator mathematically describes the edge …