A survey of automated techniques for formal software verification

V D'silva, D Kroening… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
The quality and the correctness of software are often the greatest concern in electronic
systems. Formal verification tools can provide a guarantee that a design is free of specific …

Satisfiability modulo theories

C Barrett, C Tinelli - Handbook of model checking, 2018 - Springer
Abstract Satisfiability Modulo Theories (SMT) refers to the problem of determining whether a
first-order formula is satisfiable with respect to some logical theory. Solvers based on SMT …

{Under-Constrained} symbolic execution: Correctness checking for real code

DA Ramos, D Engler - 24th USENIX Security Symposium (USENIX …, 2015 - usenix.org
Software bugs are a well-known source of security vulnerabilities. One technique for finding
bugs, symbolic execution, considers all possible inputs to a program but suffers from …

[图书][B] Decision procedures

D Kroening, O Strichman - 2016 - Springer
A decision procedure is an algorithm that, given a decision problem, terminates with a
correct yes/no answer. In this book, we focus on decision procedures for decidable first …

A decision procedure for bit-vectors and arrays

V Ganesh, DL Dill - … Aided Verification: 19th International Conference, CAV …, 2007 - Springer
STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-
vectors and arrays that has been optimized for large problems encountered in software …

Simplify: a theorem prover for program checking

D Detlefs, G Nelson, JB Saxe - Journal of the ACM (JACM), 2005 - dl.acm.org
This article provides a detailed description of the automatic theorem prover Simplify, which is
the proof engine of the Extended Static Checkers ESC/Java and ESC/Modula-3. Simplify …

Lazy satisfiability modulo theories

R Sebastiani - Journal on Satisfiability, Boolean Modeling and …, 2007 - content.iospress.com
Abstract Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a
first-order formula with respect to some decidable first-order theory T (SMT (T)). These …

Exact multiple-control Toffoli network synthesis with SAT techniques

D Große, R Wille, GW Dueck… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Synthesis of reversible logic has become a very important research area in recent years.
Applications can be found in the domain of low-power design, optical computing, and …

Bounded model checking of software using SMT solvers instead of SAT solvers

A Armando, J Mantovani, L Platania - International Journal on Software …, 2009 - Springer
C bounded model checking (cbmc) has proved to be a successful approach to automatic
software analysis. The key idea is to (i) build a propositional formula whose models …

Deciding bit-vector arithmetic with abstraction

RE Bryant, D Kroening, J Ouaknine, SA Seshia… - … 2007, Held as Part of the …, 2007 - Springer
We present a new decision procedure for finite-precision bit-vector arithmetic with arbitrary
bit-vector operations. Our procedure alternates between generating under-and over …