Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
S Sriraman, R Wise, H Singh, A Paterson… - US Patent …, 2019 - Google Patents
Disclosed are methods of generating a proximity-corrected design layout for photoresist to
be used in an etch operation. The methods may include identifying a feature in an initial …
be used in an etch operation. The methods may include identifying a feature in an initial …
Layout pattern proximity correction through edge placement error prediction
MD Tetiker, S Sriraman, AD Bailey III… - US Patent 10,534,257, 2020 - Google Patents
Disclosed are methods of generating a proximity-corrected design layout for photoresist to
be used in an etch operation. The methods may include identifying a feature in an initial …
be used in an etch operation. The methods may include identifying a feature in an initial …
Layout pattern proximity correction through fast edge placement error prediction
J Mailfert, S Sriraman, MD Tetiker - US Patent 10,254,641, 2019 - Google Patents
Disclosed are methods of generating a proximity-corrected design layout for photoresist to
be used in an etch operation. The methods may include identifying a feature in an initial …
be used in an etch operation. The methods may include identifying a feature in an initial …
Etch metric sensitivity for endpoint detection
AD Bailey III, MD Tetiker, DW Mills - US Patent 10,032,681, 2018 - Google Patents
Monitoring a geometric parameter value for one or more features produced on a substrate
during an etch process may involve:(a) measuring optical signals produced by optical …
during an etch process may involve:(a) measuring optical signals produced by optical …
Methods and apparatuses for etch profile matching by surface kinetic model optimization
MD Tetiker, S Sriraman, AD Bailey III, J Shoeb… - US Patent …, 2019 - Google Patents
Disclosed are methods of optimizing a computerized model which relates etched feature
profile on a semiconductor device to a set of independent input parameters via the use of a …
profile on a semiconductor device to a set of independent input parameters via the use of a …
Methods and apparatuses for etch profile optimization by reflectance spectra matching and surface kinetic model optimization
MD Tetiker, S Sriraman, AD Bailey III… - US Patent …, 2017 - Google Patents
Disclosed are methods of optimizing a computer model which relates the etch profile of a
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
Method of etch model calibration using optical scatterometry
Y Feng, M Musselman, AD Bailey III… - US Patent …, 2020 - Google Patents
Computer-implemented methods of optimizing a process simulation model that predicts a
result of a semiconductor device fabrication operation to process parameter values …
result of a semiconductor device fabrication operation to process parameter values …
Methods and apparatuses for etch profile optimization by reflectance spectra matching and surface kinetic model optimization
MD Tetiker, S Sriraman, AD Bailey III… - US Patent …, 2018 - Google Patents
Disclosed are methods of optimizing a computer model which relates the etch profile of a
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
Methods and apparatuses for etch profile optimization by reflectance spectra matching and surface kinetic model optimization
MD Tetiker, S Sriraman, AD Bailey III… - US Patent …, 2019 - Google Patents
Disclosed are methods of optimizing a computer model which relates the etch profile of a
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
feature on a semiconductor substrate to a set of independent input parameters (A), via the …
Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
S Sriraman, R Wise, H Singh, A Paterson… - US Patent …, 2020 - Google Patents
Disclosed are methods of generating a proximity-corrected design layout for photoresist to
be used in an etch operation. The methods may include identifying a feature in an initial …
be used in an etch operation. The methods may include identifying a feature in an initial …