Apparatus for measuring analytes including chemical sensor array

J Rothberg, T Rearick - US Patent 9,958,414, 2018 - Google Patents
US9958414B2 - Apparatus for measuring analytes including chemical sensor array - Google
Patents US9958414B2 - Apparatus for measuring analytes including chemical sensor array …

Methods and apparatus for measuring analytes

J Rothberg, W Hinz, J Davidson, A Van Oijen… - US Patent …, 2018 - Google Patents
2013-05-31 Assigned to ION TORRENT SYSTEMS INCORPORATED reassignment ION
TORRENT SYSTEMS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE …

Chemical sensor array having multiple sensors per well

JM Rothberg, KG Fife, J Bustillo, J Owens - US Patent 10,458,942, 2019 - Google Patents
In one embodiment, a device is described. The device includes a material defining a
reaction region. The device also includes a plurality of chemically-sensitive field effect …

Methods for manufacturing well structures for low-noise chemical sensors

J Bustillo, S Li - US Patent 9,841,398, 2017 - Google Patents
In one implementation, a method for manufacturing a chemical detection device is
described. The method includes forming a chemical sensor having a sensing surface. A …

Chemically sensitive sensor with lightly doped drains

KG Fife - US Patent 9,960,253, 2018 - Google Patents
A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance
between a gate and an electrode of the chemical sensitive sensor. The lightly doped region …

Automatic detection of change in PLL locking trend

TH Tsai, CH Chang - US Patent 9,853,807, 2017 - Google Patents
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …

Hybrid phase lock loop

TH Tsai, RB Sheen, CH Chang, CH Hsieh - US Patent 10,164,649, 2018 - Google Patents
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …

PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications

FW Kuo, CP Jou, LC Cho, C Huan-Neng… - US Patent …, 2019 - Google Patents
US10171089B2 - PVT-free calibration function using a doubler circuit for TDC resolution in
ADPLL applications - Google Patents US10171089B2 - PVT-free calibration function using …

High data rate integrated circuit with power management

KG Fife, J Yang - US Patent 10,077,472, 2018 - Google Patents
A sensor device includes a sensor array and a flow cell in fluid communication with the
sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor …

Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces

NA Kurd, TP Thomas - US Patent 8,736,328, 2014 - Google Patents
Low power, jitter and latency clocking with common reference clock signals for on-package
input/output interfaces. A filter phase locked loop circuit in a master device on a first die …