Design and power dissipation consideration of PFAL CMOS V/S conventional CMOS based 2: 1 multiplexer and full adder
With the integration of circuits, number of gates and transistors are increasing per chip area.
However with integration in every digital circuit, the energy due to switching of gate doesn't …
However with integration in every digital circuit, the energy due to switching of gate doesn't …
Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay
K Gavaskar, MS Narayanan, MS Nachammal… - Journal of Ambient …, 2022 - Springer
Static random access memory power and speed dissipation are the significant factor in most
of the electronic applications, which prompts numerous plans with the power utilization of …
of the electronic applications, which prompts numerous plans with the power utilization of …
Development of LPG leakage detection alert and auto exhaust system using IoT
K Gavaskar, D Malathi, G Ravivarma… - … on Electrical Energy …, 2021 - ieeexplore.ieee.org
Security play a significant part in this day and age and it is fundamental that acceptable
wellbeing frameworks are to be actualized in spots of schooling and work. Gas spillage is …
wellbeing frameworks are to be actualized in spots of schooling and work. Gas spillage is …
Design and Simulation of New High Speed, Low Power D-Flip-Flops, Implemented Using Graphene Nanoribbon and Carbon Nanotube Field Effect Transistors
H Fereidounpour, N Yasrebi, H Pakniat - Iranian Journal of Science and …, 2024 - Springer
Abstract A novel 13-transistor, low-power true single-phase clocked (TSPC) flip-flop design
is proposed which improves clock loading, power consumption, and performance. The …
is proposed which improves clock loading, power consumption, and performance. The …
A fresh design of power effective adapted vedic multiplier for modern digital signal processors
K Gavaskar, D Malathi, G Ravivarma, VK Devi… - Wireless Personal …, 2022 - Springer
Abstract Digital Signal Processors play an unavoidable portion in modern-day
communication. The Multiply Accumulate (MAC) is a crucial component of modern signal …
communication. The Multiply Accumulate (MAC) is a crucial component of modern signal …
Constant delay systolic binary counter with variable size cellular automaton based prescaler
V Chioktour, A Kakarountas - Computers & Electrical Engineering, 2021 - Elsevier
Abstract An One-Dimension (1D) Cellular Automaton (CA) is studied as a generator for the
radix-2 sequence, presenting suitable characteristics for the design of a fast and constant …
radix-2 sequence, presenting suitable characteristics for the design of a fast and constant …
Even-Odd Sorting Network for Fast Binary Counters
RP Vidyadhar, LA Devi, D Sagar… - 2023 4th International …, 2023 - ieeexplore.ieee.org
In various digital signal processing devices, the efficiency of data multiplication is a common
performance limiter and the critical route includes the parallel summing of multiple …
performance limiter and the critical route includes the parallel summing of multiple …
[PDF][PDF] Design of CMOS Circuit Based on NAND Function at 150nm Channel Length for Low-Power and High-Speed IC Fabrication
S Roy, S Roy, A Adhikary, A Dey, S Pattanayak, S Bari - academia.edu
In this paper the low-power and high-speed design approach of one Complementary Metal
Oxide Semiconductor (CMOS) circuit based on NAND function has been reported. The …
Oxide Semiconductor (CMOS) circuit based on NAND function has been reported. The …