Coarse-grained reconfigurable architectures for radio baseband processing: A survey

Z Hassan, A Ometov, ES Lohan, J Nurmi - Journal of Systems Architecture, 2024 - Elsevier
Emerging communication technologies, such as 5G and beyond, have introduced diverse
requirements that demand high performance and energy efficiency at all levels …

Energy efficient design of coarse-grained reconfigurable architectures: Insights, trends and challenges

E Aliagha, D Göhringer - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
Coarse-Grained Reconfigurable Architectures (CGRAs) are promising solutions to achieve
more performance with the end of Moore's law. Thanks to word-level programmability, they …

A low-power transprecision floating-point cluster for efficient near-sensor data analytics

F Montagna, S Mach, S Benatti… - … on Parallel and …, 2021 - ieeexplore.ieee.org
Recent applications in low-power (1-20 mW) near-sensor computing require the adoption of
floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this …

Rewriting History: Repurposing Domain-Specific CGRAs

J Woodruff, T Koehler, A Brauckmann… - arXiv preprint arXiv …, 2023 - arxiv.org
Coarse-grained reconfigurable arrays (CGRAs) are domain-specific devices promising both
the flexibility of FPGAs and the performance of ASICs. However, with restricted domains …

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

B de Bruin, K Vadivel, M Wijtvliet… - ACM Transactions on …, 2024 - dl.acm.org
Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT)
domain require complex on-device signal analysis and data reduction to maximize energy …

RMSRM: real-time monitoring-based self-reconfiguration mechanism in reconfigurable PE array

K Yang, L Jiang, R Shan, K Li, X Cui - The Journal of Supercomputing, 2024 - Springer
Modern applications need to flexibly adjust the processing process according to the different
environments and real-time processing, thus putting forward higher requirements for the …

IEEE754 Binary32 floating-point logarithmic algorithms based on Taylor-series expansion with mantissa region conversion and division

J Wei, A Kuwana, H Kobayashi… - IEICE Transactions on …, 2022 - search.ieice.org
In this paper, an algorithm based on Taylor series expansion is proposed to calculate the
logarithm (log 2 x) of IEEE754 binary32 accuracy floating-point number by a multi-domain …

Acceleration for the many, not the few

J Woodruff - 2024 - era.ed.ac.uk
Although specialized hardware promises orders of magnitude performance gains, their
uptake has been limited by how challenging it is to program them. Hardware accelerators …

[PDF][PDF] Design of Energy‐Efficient CGRA‐based Systems

E de Bruin - 2024 - research.tue.nl
Technological advances over the last few decades enabled us to equip billions of low‐cost
mobile and embedded sensor devices with compute capabilities using general‐purpose …

HDL Programming and Sequential Circuitry for Multi-Core RISC-V Processor

AK DB, B Bairwa, B Vamsidath, V Ujwal… - … on Smart Systems …, 2023 - ieeexplore.ieee.org
This paper presents a detailed description of the design of a 64-bit RISC-V processor that
implements the RISC-VISA using Verilog hardware descriptive language. The design is …