We present a novel approach for synthesizing photo-realistic images of people in arbitrary
poses using generative adversarial learning. Given an input image of a person and a …

Fast yield ramping in a new technology to meet aggressive time-to-market deadlines
requires a comprehensive design and fabrication methodology for silicon test structures that …

At advanced technology nodes, complex interactions between layout features and the
process can lead to manufacturability issues that reduce yield. Due to the huge number of …

Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has
emphasized the diagnosability properties of a specific class of regular circuits called …

The benefits of the continued progress in integrated circuit manufacturing have been
numerous, most notably in the explosion of computing power in devices ranging from cell …

Logic test chips are a key component of the yield learning process, which aim to investigate
the yield characteristics of actual products that will be fabricated at high volume …

The relentless scaling of integrated circuits (IC) are bringing challenges to the manufacturing
process. The decreasing distance between transistors and complicated layout features …

Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has
achieved optimal testability for static fault models. This work explores enhancements to the …

As semiconductor manufacturing progresses to smaller process nodes, it is becoming
increasingly difficult to climb the yield learning curve rapidly. The rate of yield learning …

A new product-like test chip developed by engineers at Carnegie Mellon University
overcomes the current limitations in conventional test chip design. This article discusses the …