PUF-based authentication
In the context of hardware systems, authentication refers to the process of confirming the
identity and authenticity of chip, board and system components such as RFID tags, smart …
identity and authenticity of chip, board and system components such as RFID tags, smart …
[图书][B] Synthesis of quasi-delay-insensitive datapath circuits
WB Toms, D Edwards - 2006 - apt.cs.manchester.ac.uk
As the number of transistors on Integrated Circuits grows VLSI systems are becoming
increasingly complex. In all but the highest performance systems, designers are turning to …
increasingly complex. In all but the highest performance systems, designers are turning to …
Asynchronous design—Part 2: Systems and methodologies
SM Nowick, M Singh - IEEE Design & Test, 2015 - ieeexplore.ieee.org
This two-part article aims to provide both a short historical and technical overview of
asynchronous design, as well as a snapshot of the state of the art. Part 1 covered …
asynchronous design, as well as a snapshot of the state of the art. Part 1 covered …
The influences of social networks on phishing vulnerability
K Coronges, R Dodge, C Mukina… - 2012 45th Hawaii …, 2012 - ieeexplore.ieee.org
Phishing is a form of electronic deception in which an attacker tries to cause the recipient to
do something or disclose data that they likely would not normally do by mimicking a …
do something or disclose data that they likely would not normally do by mimicking a …
VLSI Implementation of a Distributed Algorithm for Fault‐Tolerant Clock Generation
G Fuchs, A Steininger - Journal of Electrical and Computer …, 2011 - Wiley Online Library
We present a novel approach for the on‐chip generation of a fault‐tolerant clock. Our
method is based on the hardware implementation of a tick synchronization algorithm from …
method is based on the hardware implementation of a tick synchronization algorithm from …
[图书][B] Asynchronous circuit stacking for simplified power management
The increasingly complex digital integrated circuits (ICs) often incorporate multiple power
domains, thereby requiring multiple voltage converters to produce the corresponding supply …
domains, thereby requiring multiple voltage converters to produce the corresponding supply …
M-of-N code decomposition for indicating combinational logic
WB Toms, DA Edwards - 2010 IEEE Symposium on …, 2010 - ieeexplore.ieee.org
Self-timed circuits present an attractive solution to the problem of process variation.
However, implementing self-timed combinational logic is complex and expensive. In …
However, implementing self-timed combinational logic is complex and expensive. In …
Fault-tolerant distributed algorithms for on-chip tick generation: concepts, implementations and evaluations
G Fuchs - 2009 - repositum.tuwien.at
In the course of this thesis a novel approach for the on-chip generation of a fault-tolerant
clock is developed. At first this is motivated by the fact that with shrinking feature sizes and …
clock is developed. At first this is motivated by the fact that with shrinking feature sizes and …
[PDF][PDF] Two-Level Hazard-Free Logic Minimization of Speed-Independent Extended Burst-Mode Controllers
DL Oliveira, LA Faria - Simpósio de Aplicações Operacionais em Áreas …, 2015 - sige.ita.br
Several algorithms of hazard-free logic minimization were proposed for extended burst-
mode asynchronous controllers that operate in the generalized fundamental mode (GFM) …
mode asynchronous controllers that operate in the generalized fundamental mode (GFM) …
[图书][B] Design and performance optimization of asynchronous networks-on-chip
W Jiang - 2018 - search.proquest.com
As digital systems continue to grow in complexity, the design of conventional synchronous
systems is facing unprecedented challenges. The number of transistors on individual chips …
systems is facing unprecedented challenges. The number of transistors on individual chips …