PAM: a novel performance/power aware meta-scheduler for multi-core systems

M Banikazemi, D Poff, B Abali - SC'08: Proceedings of the 2008 …, 2008 - ieeexplore.ieee.org
Sharing resources such as caches and main memory bandwidth in multi-core systems
requires a more sophisticated scheduling scheme. PAM is a low-overhead, user-level meta …

DrMP: Mixed precision-aware DRAM for high performance approximate and precise computing

X Zhang, Y Zhang, BR Childers… - 2017 26th International …, 2017 - ieeexplore.ieee.org
Recent studies showed that DRAM restore time degrades as technology scales, which
imposes large performance and energy overheads. This problem, prolonged restore time …

PREMSim: A resilience framework for modeling traditional and emerging memory reliability

D Kline, S Longofono, S Ollivier… - 2019 IEEE 27th …, 2019 - ieeexplore.ieee.org
Scaling limitations of conventional and emerging memories has provided the impetus for the
increased focus on reliability techniques to overcome associated physical limitations of non …

Recovering from biased distribution of faulty cells in memory by reorganizing replacement regions through universal hashing

J Jun, KH Choi, H Kim, SH Yu, SW Kim… - ACM Transactions on …, 2017 - dl.acm.org
Recently, scaling down dynamic random access memory (DRAM) has become more of a
challenge, with more faults than before and a significant degradation in yield. To improve the …

Addressing prolonged restore challenges in further scaling DRAMs

X Zhang - 2017 - search.proquest.com
As the de facto memory technology, DRAM has enjoyed continuous scaling over the past
decades to keep performance growth and capacity enhancement. However, DRAM further …

Fault tolerance technique offlining faulty blocks by heap memory management

J Jun, Y Paik, GI Min, SW Kim, Y Han - ACM Transactions on Design …, 2019 - dl.acm.org
As dynamic random access memory (DRAM) cells continue to be scaled down for higher
density and capacity, they have more faults. Thus, DRAM reliability becomes a major …