Data prefetching hides memory latency by predicting and loading necessary data into cache
beforehand. Most prefetchers in the literature are efficient for specific memory address …

The frontend stalls caused by instruction and BTB misses are a significant source of
performance degradation in server processors. Prefetchers are commonly employed to …

Managing tail latency is a primary challenge in designing large-scale Internet services.
Queuing is a major contributor to end-to-end tail latency, wherein nominal tasks are …

Offset prefetching has been recently proposed as a lowoverhead yet high-performance
approach to eliminate data cache misses or reduce their negative effect. In offset …

The Register File (RF) is a critical structure in Graphics Processing Units (GPUs) responsible
for a large portion of the area and power. To simplify the architecture of the RF, it is …

In this paper, we present NESTA, a specialized Neural engine that significantly accelerates
the computation of convolution layers in a deep convolutional neural network, while …

With increasing core counts and multiple levels of cache memories, scaling multi-threaded
and task-level parallel workloads is continuously becoming a challenge. A key challenge to …

Graphics Processing Units (GPUs) employ large register files to accommodate all active
threads and accelerate context switching. Unfortunately, register files are a scalability …

As deep learning has produced dramatic breakthroughs in many areas, it has motivated
emerging studies on the combination between neural networks and cache replacement …

Recent research revisits pairwise-correlating data prefetching due to its extremely low
overhead. Pairwise-correlating data prefetching, however, cannot accurately detect where …