We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator
based on an ingress-queued wormhole router architecture. The parallel simulation engine …

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on
an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel …

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based
on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine …

Network on chip (NoC) is a scalable interconnection architecture for ever increasing
communication demand between processing cores. However, in nanoscale technology size …

This work presents the architecture and ASIC implementation of Hermes-AA, a flexible fully
asynchronous network on chip router employing an adaptive routing algorithm. Hermes-AA …

While quality-adaptable applications are gaining increased popularity on embedded
systems (especially multimedia applications), efficient scheduling techniques are necessary …

The partially adaptive routing plays an important role in the performance of Network-on-Chip
(NoC). It uses information of the network to select a better path to deliver a packet. However …

Networks-on-chips (NoCs) are gaining in popularity as replacement for shared medium
interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips, and …

The effectiveness of an adaptive router in a Network on Chip (NoC) is evaluated by the
selection metric it uses and its impact on overall performance. In this paper, we propose a flit …

If the route computation operation in an adaptive router returns more than one output
channels, the selection strategy chooses one from them based on the congestion metric …