Design of Efficient Phase Locked Loop for Low Power Applications

CK Pothina, NP Singh, JL Prasanna… - Engineering …, 2023 - mdpi.com
The phase-locked loop is a technique that has contributed significantly to technological
advancements in many applications in the fast-evolving digital era. In this paper, a Phase …

Design and implementation of low power phase frequency detector for phase lock loop

KP Thakore, K Shah… - 2019 3rd International …, 2019 - ieeexplore.ieee.org
This paper presents a low power phase frequency detector for Phase lock loop. A presented
Low power Phase Frequency Detector is implemented in Cadence virtuoso environment …

Design of frequency synthesizer for wireless communication

R Gatti, RK Amrutha, AG Raghuveer… - 2017 2nd IEEE …, 2017 - ieeexplore.ieee.org
Modems play a vital role in the field of communication, Suitable and stable carrier frequency
is required for any efficient modulation process. This paper proposes a method of generating …

Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software

MSN Dandare, MAH Deshmukh - Journal of Science & Technology (JST), 2018 - jst.org.in
Digital Phase locked loop (DPLL) is one of the most important devices in almost all the
electronic systems. This paper introduces the design of DPLL using sub-micron 45nm …

Fixed-Pole active PI filter design for high frequency nonlinear PLL models

SJA Bakar, NS Ahmad, P Goh - Journal of Advanced …, 2019 - jamt.utem.edu.my
A Phase-locked loop (PLL) is a basic control system that attempts to produce an output
waveform that can match with the input reference signal in the shortest time possible. A filter …

Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications

AJ Douglass, SP Khatri - 2018 IEEE 36th International …, 2018 - ieeexplore.ieee.org
Ring-based Resonant Standing Wave Oscillators (RRSWOs) have been shown to be a
powerful technique to perform low power clock generation and distribution for high-speed …

Projeto de Malha de Captura de Fase Autocalibrável

RAM Teixeira - 2018 - repositorio-aberto.up.pt
A significativa evolução das tecnologias da microeletrónica e os cada vez maiores níveis de
integração de semicondutores por unidade de área, permitem a integração de circuitos …

Reduction of Phase Noise and Lock Time in Low Power Phase Lock Loop (PLL)

A Kumar, SS Ojha, S Akashe - Journal of Computational and …, 2018 - ingentaconnect.com
Phase Lock Loops (PLL) are used in many areas of Radio Frequency (RF) project such as
for Frequency Modulation/Demodulation, Clock Recovery, Signal Re-Constitution, but …

[引用][C] Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications

AJ Douglass - 2019

[引用][C] Approximation of Digital PLL using CMOS Technology

R Arya, B Kumar Singh… - … of Computing and …, 2024 - University of Bahrain