DRAM technology scaling has the undesirable side effect of degrading cell reliability. One
such concern of deeply scaled DRAMs is the increased coupling between adjacent cells …

As technology process node scales down, on-chip SRAM caches lose their efficiency
because of their low scalability, high leakage power, and increasing rate of soft errors …

The growth in data needs of modern applications has created significant challenges for
modern systems leading to a “memory wall.” Spintronic Domain-Wall Memory (DWM) …

Recent development in memory technologies has introduced Spin-Transfer Torque
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …

The advancement of Silicon CMOS technology has led information technology innovation for
decades. However, scaling transistors down according to Moore's law is almost reaching its …

Spintronic domain wall memories (DWMs) are prone to alignment faults, which cannot be
protected by traditional error correction techniques. To solve this problem, we propose a …

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for
static random-access memories in large last-level on-chip caches due to their higher density …

Spintronic domain-wall memories (DWMs) offer improved memory density and energy
compared to conventional memories, but are susceptible to shifting faults. We propose …

DRAM cells in deeply scaled CMOS confront significant challenges to ensure reliable
operation. Parasitic capacitances induced by certain bit storage patterns, or bad patterns …

Neural networks have been successfully used in many applications. Due to their
computational complexity, it is difficult to implement them on embedded devices. Neural …